Challenges Mount For Patterning And Masks

Semiconductor Engineering sat down to discuss and photomask trends with Uday Mitra, vice president and chief technology officer for the Etch Business Unit at Applied Materials; Pawitter Mangat, senior manager and deputy director for EUV lithography at GlobalFoundries; Aki Fujimura, chief executive at D2S; Naoya Hayashi, a fellow at Dai Nippon Printing (DNP); and Mike Rieger, senior director of engineering at Synopsys. What follows are excerpts of that discussion.

SE: In part 1 and part 2 of the roundtable, we discussed patterning. Let’s move to the photomask side of the equation. For years, the industry has used single-beam e-beam tools for mask writing. Now, IMS Nanofabrication is in beta-site testing with a multi-beam e-beam mask writer. What does that bring to the party?

Fujimura: The mask community will undergo an exciting time in the next couple of years, maybe in the next five years. It’s about to make huge contributions to the world of semiconductor manufacturing. Mask making has always done it, but it’s always been kind of a subservient player. I’ve already mentioned multi-beam mask writing. That’s a big thing. That’s not a big thing just when it happens. Because everybody thinks multi-beam mask writing will happen, people are investing more as a result of the technology. Dose control is one example. People are also looking at very complex patterns that you can exploit with inverse lithography. The OPC community can do more creative things without the constraint of the mask being able to write in a reasonable time. There is a lot of activity in the mask inspection side to handle these complex shapes. That must keep some people up at night. There are also very slow resists that can be used to gain accuracy. That’s without a penalty in write times. That’s huge. Regarding negative resists, the mask community has always wanted to use that. But again, it has a problem with precision. That problem can be solved.

Rieger: The emergence of the multi-beam writer is going to give a lot more flexibility to our ability to synthesize the optimum mask pattern. If you want to get that extra percentage of the process window, you can leverage those extra degrees of freedom that you can pattern on the mask to get a better quality image on the wafer.

SE: Will single-beam disappear as a result of multi-beam?

Fujimura: Multi-beam is exciting for the future, but it’s not a reality today. The VSB-related activities have to continue on.

SE: What else is going on in the mask shop?

Fujimura: The natural process of the mask is that the feature sizes are getting smaller and smaller. What’s also happening in the world of advanced masks is that the sidewall angle is not the same everywhere. Depending on what shape it is, and what the dose margin is, it’s changing. It’s no longer sufficient to look at the 2D image. We really need to look at the 3D image.

Mitra: There are two parts here. First, one is the fabrication of the masks. For example, we have multi-patterning. And now, there are so many different masks to deal with. That translates into CD control and variation-etch control. And just like the wafer side, the budgets are getting smaller and smaller. Second, we have EUV, which is making it a little bit more challenging. There are additional constraints on the mask. That’s on the fabrication side. On the inspection side, there are many, many challenges, both on regular masks as well as EUV masks. Even the blanks themselves are becoming challenging. The question is how do you inspect the defects on the mask blanks?

Mangat: From the mask side, the one thing that we are seeing is the mask data volumes. Tons of data management is required. But the challenge is that everybody thinks the mask is a commodity. What people need to realize is how critical the mask is to the entire industry. People need to look at the investment the mask takes to become productized. Meanwhile, regarding materials control, that must be watched very closely. E-beam write times for these advanced nodes are challenging. Multi-beam would be good to have. And as we go to these tight features, and countless masks, the traditional way we do cleans must change. Now, you are looking at a lot more minor things.

Hayashi: There are a number of challenges, especially in metrology. The measurement numbers per mask are exploding. We may measure the mask at 200 places, but some customers want to measure 5,000 places.

Mangat: What you are measuring is also different. Before, it was tip to tip and tip to side. The numbers were assumed to be there. Now, for nanometer overlay patterning, there are a different set of requirements that are emerging. This is because optical lithography is continuing and the specs are getting tighter.

Hayashi: There is not only the CD, but also the registration overlay. Normally, we measure the overlay alignment mark outside the chip. Now, customers want the exact measurement inside the die. It could be in a thousand places. The captive mask shop will know about the hot spot area. But for the merchant mask shop, they kind of have one number or spec everywhere, plus or minus one nanometer.

SE: What about metrology and inspection in the mask shop?

Hayashi: We need a cost-effective metrology system to realize 5,000 different measurements in the mask within several hours. Currently, it takes two days. We currently use a CD-SEM. But the CD-SEM is quite slow. If we could use a multiple beam inspection or imaging system as a high-throughput CD measurement system, that could be a good thing.

Fujimura: Multi-beam inspection is one possibility. In-between, there is multi-beam CD-SEM inspection technology. That could take some innovation for someone to step up to do it.

Hayashi: Of course, the mask inspection system is very expensive. That’s almost the same cost as the writing tool. Also, we have to use the inspection tool in multiple passes. So for inspection, especially defect inspection, the costs are quite high.

SE: Let’s look into the future and make some predictions. What type of tool and patterning techniques will chipmakers use at 7nm and 5nm?

Fujimura: If I were to bet, I would say that it would be a mixture of approaches. There might be a bifurcation. Different types of applications may require different things. So at 7nm and 5nm, different people are going to have different strategies. That’s not necessarily good for the industry, because the investments get divided.

Rieger: It will be a hybrid approach. As the efficiencies improve in the power source, EUV may come in. EUV will most likely be done in combination with 193nm immersion for cut patterns or for guiding self-aligned contacts. That would be my expectation at 7nm. It’s a combination of both.

Mitra: Initially, EUV will probably come in for a couple of layers, just to minimize the risk. Then, EUV may be used for a few other layers at the next node. 193nm will remain for the pitch division and line and space. EUV will come in for contacts, maybe metal one. Later on, it’s really for the cuts and the holes. Along with lithography, you will see a lot of innovation in the materials. This will be deposition, removal and etch. They will actually enable and support lithography.

Mangat: For 7nm, we will probably start off with (ASML’s) NXT version. So you will start with the optical product. And then, that will transition into some NXE EUV version. That could be for one critical and two critical layers. At 7nm, we will see both flavors. But first, it’s optical and then a hybrid approach with EUV. For 5nm, I think both will happen.

Hayashi: Technically, at 7nm, optical will still be the mainstream technology. But, of course, it also depends on the device and application. If the industry can improve the defectivity and overlay, then maybe nanoimprint is inserted in other areas.

Mangat: There also might be a change in the paradigm. Rather than a system-on-a-chip, you could have a system-on-a-die. You could have multiple functions that are interconnected that reduce the cost of lithography. In effect, you are stacking chips up in a 3D fashion. This is another opportunity.

SE: And finally, at the recent SPIE event, Intel senior fellow Yan Borodovsky said the biggest challenge to continue IC scaling is not multi-patterning, but rather edge placement error. Meanwhile, Burn Lin of TSMC said that overlay could be the limiting factor. Any thoughts?

Mitra: Edge placement error and overlay are clearly going to be challenging. In pitch division, you can do it 32 times. But getting the patterns exactly where you want them to be is the fundamental challenge. At 5nm, it becomes very, very big.

Mangat: Clearly, the lithography resolution and the overlay control are coming head to head as we move to the next nodes.