Chip Industry Technical Paper Roundup: Feb. 4

Mixed-precision DL inference; CXL memory pooling; processing-using-DRAM; Apple CPU vulnerabilities; pager and walkie-talkie attacks; ultranarrow semiconductor WS2 nanoribbon FETs; line width roughness; indium nitrate resists.

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New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Controlling Speckle Contrast Using Existing Lithographic Scanner Knobs to Explore the Impact on Line Width Roughness Samsung, ASML and Sungkyunkwan University
StruM: Structured Mixed Precision for Efficient Deep Learning Hardware Codesign Intel
Octopus: Scalable Low-Cost CXL Memory Pooling University of Washington, Microsoft Azure and Columbia University
Proteus: Achieving High-Performance Processing-Using-DRAM via Dynamic Precision Bit-Serial Arithmetic ETH Zurich, Cambridge University, Universidad de Córdoba, Univ. of Illinois Urbana-Champaign and NVIDIA Research
Apple CPU Vulnerabilities-two papers:
1) FLOP: Breaking the Apple M3 CPU via False Load Output Predictions and
2) SLAP: Data Speculation Attacks via Load Address Prediction on Apple Silicon
Georgia Tech and Ruhr University Bochum
When Everyday Devices Become Weapons: A Closer Look at the Pager and Walkie-talkie Attacks University of Florida
Ultranarrow Semiconductor WS2 Nanoribbon Field-Effect Transistors Chalmers University of Technology
Sensitivity and contrast of indium nitrate hydrate resist evaluated by low-energy electron beam and extreme ultraviolet exposure UT Dallas

Find all technical papers here.



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