Chip Industry Technical Paper Roundup: June 9

Customizing a LLM for VHDL design; HW-centric analysis of DeepSeek’s multi-head latent attention; high-density polymer waveguides with silicon photonics for CPO; RISC-V energy efficiency of superscalar OoO execution; V-NAND PUFs; bond wave speed in wafer bonding; HW-efficient attention for fast decoding; PFAS modeling in IC manufacturing.

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New technical papers recently added to Semiconductor Engineering’s library:

Name of Paper Research Organizations
Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors IBM
Hardware-Centric Analysis of DeepSeek’s Multi-Head Latent Attention KU Leuven
Low-Loss Integration of High-Density Polymer Waveguides with Silicon Photonics for Co-Packaged Optics imec and Ghent University
Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution ETH Zurich, Università di Bologna and Univ. Grenoble Alpes, Inria
Concealable physical unclonable functions using vertical NAND flash memory Seoul National University and SK hynix
Factors determining bond wave speed in wafer bonding Yokohama National University, Tokyo Electron Kyushu Limited and ANVOS Analytics
Modeling PFAS in Semiconductor Manufacturing to Quantify Trade-offs in Energy Efficiency and Environmental Impact of Computing Systems Harvard University and MBZUAI
Hardware-Efficient Attention for Fast Decoding Princeton University

Find more semiconductor research papers here.



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