Chip Industry Technical Paper Roundup: Sept. 24

PIM memory management; carbon nanotube FETs; high-degree polynomial gradients in memory; STT-MRAM; neuro-symbolic AI HW architecture; state of the semi industry; GAAFETs.

popularity

New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
PIM-MMU: A Memory Management Unit for Accelerating Data Transfers in Commercial PIM Systems KAIST
Overcoming Ambient Drift and Negative-Bias Temperature Instability in Foundry Carbon Nanotube Transistors MIT, Stanford University, Carnegie Mellon University and Analog Devices
2024 State of the U.S. Semiconductor Industry SIA
Computing high-degree polynomial gradients in memory UCSB, HP Labs, Forschungszentrum Juelich GmbH, and RWTH Aachen Univ.
Enhancing Security and Power Efficiency of Ascon Hardware Implementation with STT-MRAM CEA, Leti, Université Grenoble Alpes, CNRS, and Spintec
Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture Georgia Tech, UC Berkeley, and IBM Research
Impact of Strain on Sub-3 nm Gate-all-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach Hanyang University and Alsemy Inc.

More Reading
Technical Paper Library home



Leave a Reply


(Note: This name will be displayed publicly)