GPU energy efficiency; logic locking; HLS LLMs; thin films reflectometry and TEM; silicon quantum dot errors; DL compiler for AI chips; low leakage IGZO for neuromorphic; HW CEE for virtual memory; GPU to GPU communications.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Virgo: Cluster-level Matrix Unit Integration in GPUs for Scalability and Energy Efficiency | UC Berkeley |
| Exploring GPU-to-GPU Communication: Insights into Supercomputer Interconnects | Sapienza University of Rome, University of Trento, Vrije Universiteit Amsterdam, ETH Zurich, CINECA, University of Antwerp, IBM Research Europe, HPE Cray, and NVIDIA |
| A Hardware-Based Correct Execution Environment Supporting Virtual Memory | Korea University, Korea Advanced Institute of Science and Technology et al. |
| A tunable multi-timescale Indium-Gallium-Zinc-Oxide thin-film transistor neuron towards hybrid solutions for spiking neuromorphic applications |
imec, CSIC Universidad de Sevilla, and Sungkyunkwan University |
| Late Breaking Results: On the One-Key Premise of Logic Locking | Synopsys |
| Scaling Deep Learning Computation over the Inter-Core Connected Intelligence Processor | UIUC and Microsoft Research |
| Assessment of the errors of high-fidelity two-qubit gates in silicon quantum dots | UNSW, Diraq, Sandia National Laboratories, Keio University, Leibniz-Institut für Kristallzüchtung and others |
| Are LLMs Any Good for High-Level Synthesis? | University of Arizona |
| Interface sharpness in stacked thin film structures: a comparison of soft X-ray reflectometry and transmission electron microscopy | Physikalisch-Technische Bundesanstalt (PTB), imec, and Thermo Fisher Scientific |
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