Directed Self-Assembly Gains Momentum

At last year’s SPIE Advanced Lithography symposium, directed self-assembly (DSA) grabbed the spotlight as chipmakers provided the first glimpse of their initial work and results with the technology.

The results were stunning, thereby propelling DSA from a curiosity item to a possible patterning solution for next-generation devices. Last year, in fact, GlobalFoundries, IBM, Intel and Samsung demonstrated test chips using DSA, a complementary and disruptive patterning technology that enables fine pitches through the use of self-assembling block copolymers.

At this year’s SPIE event, however, it was a different story. The event featured a plethora of DSA papers, but IBM was the only chipmaker that talked about test chips. GlobalFoundries and Intel gave papers, although the presentations had little to do with DSA-enabled chips. And Samsung inexplicably canceled its anticipated paper on DSA at the last minute.

So, is the industry giving up on DSA? No. DSA is making remarkable progress and is gaining momentum in the market. At SPIE, for example, Intel and others formed a new DSA consortium. In addition, GlobalFoundries, IBM, Samsung and TSMC are still working on DSA in R&D, but vendors are keeping their cards close to the vest.

Still, the consensus among chipmakers is that DSA could be ready for high-volume manufacturing at 7nm or 5nm. “Intel is talking about an introduction at the 5nm node. I have the feeling that the memory people could introduce it sooner, maybe in 2015 to 2016,” said Serge Tedesco, lithography program manager at CEA-Leti, which is also part of the new DSA consortium with Intel.

As before, the industry is still getting its arms around the problems with DSA. There are still questions about defects, integration schemes and the design infrastructure. And until the problems are solved, risk-adverse chipmakers are reluctant to put DSA into production.

“People are getting more serious about DSA,” said Akihisa Sekiguchi, corporate vice president and deputy general manager of Tokyo Electron Ltd. (TEL), one of the key suppliers of track and other equipment for DSA production. “DSA is still something for the future. It is still not at a point where people are comfortable in plugging it into manufacturing. However, it’s a serious contender. And there are enough people with enough clout to make it happen.”

But DSA does face some stiff competition. It’s just one of several and competing multiple patterning schemes for 10nm and beyond. The other candidates include the traditional multiple exposure schemes. The new kid on the block is self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP).

SADP/SAQP, which has enabled NAND to scale to the 1xnm node regime, is now moving into the logic space. “Self-aligned double patterning came up very quickly (in NAND),” said Christopher Bencher, a member of the technical staff at Applied Materials. “If that is an indicator, and if that indicator is uniform across the industry, that will pull the rug out from under DSA.”

What is DSA?
DSA is not a next-generation lithography (NGL) tool per se, but rather it is a complementary technology. When used in conjunction with a pre-pattern that automatically directs the orientation of the block copolymers, DSA can reduce the pitch of the final printed structure.

DSA is also disruptive and threatens the status quo, because the process isn’t dependent on costly lithography. In fact, DSA makes use of existing lithography tools. All the key processing steps are conducted in a wafer track system.

Using 193nm immersion lithography, DSA has demonstrated the ability to pattern structures down to 12.5nm. The industry also is working on next-generation, high chi materials, which could extend the technology beyond 12.5nm, thereby pushing out the need for extreme ultraviolet (EUV) lithography.

By most accounts, though, DSA will not appear until 7nm. At 7nm, the industry is looking at going down one of two paths in patterning—EUV with multiple patterning or 193nm immersion with multiple patterning.

The industry would prefer to use EUV at 7nm, but EUV would then be processing wafers below its targeted wavelength of 13.5nm. So in theory, EUV would require a multiple patterning scheme. But in fact, EUV with double patterning is 2.5 times the cost per wafer, as compared to 193nm immersion with double patterning, according to a presentation from Stephen Renwick, senior research scientist at Nikon.

Another expensive option is to extend 193nm immersion and multiple patterning down to 7nm. For both EUV and 193nm immersion, there are three types of multiple patterning schemes. The first type is the traditional multiple exposure schemes, such as litho-etch-litho-etch (LELE). The second type includes SADP and SAQP. And finally, DSA is the dark horse.

To make it more complex, each multiple patterning scheme is competing for a different part of the logic structure. In logic, there are four critical pieces that require patterning—fin/act; gate; metal; and via. DSA is competing with the other schemes for fins, metals and vias.

Just where and when DSA will appear remains the subject of hot debate. “DSA has some potential, but it only has some limited applications,” said Dean Freeman, an analyst with Gartner. “For contact holes, it looks like it has some possibilities. For lines and spaces, I am not sure it has applications for quite awhile.”

Others have a different viewpoint. “We are in good shape to have (a DSA) process ready for 7nm,” said Moshe Preil, manager of emerging lithography and tools at GlobalFoundries. “The most natural early adoption for DSA would the fin layer, and possibly the poly layer, because that’s unidirectional. The big question these days at 7nm is will the metal be unidirectional or will it have to stay bidirectional? And if it is unidirectional, can we keep it on a single pitch? In any case, what we really need is a lot of work done on the design side to have people figure out how to design working devices with these patterns and having that ready by 7nm.”

Still others are more bullish. DSA has fewer process steps than other multiple patterning schemes, making it a more cost-effective solution, said Ralph Dammel, chief technology officer for AZ Electronic Materials. “There are still a lot of things that have to come together,” Dammel said. “We are on track to see implementation of DSA for pilot lines for the first half of this year. We are talking about real devices and fully integrated process flows.”

DSA makes breakthroughs
In fact, Albany Nanotech, CEA-Leti, IBM and Imec have recently set up R&D pilot lines for DSA. The latest pilot line is currently being set up by PLACYD, a new European-funded consortium. It includes Arkema, ASML, CEA-Leti, Intel, Mentor Graphics and STMicroelectronics.

The pilot line will be set up at Arkema’s research center in France. Initially, the pilot line will use Arkema’s DSA materials. High chi materials will be developed at a later stage. In addition, the group will develop a DSA infrastructure, which includes metrology tools and EDA software, said CEA-LETI’s Tedesco.

DSA is also making progress on other fronts. At SPIE, for example, GlobalFoundries took a step in solving one of the biggest problems with DSA—defects. Last year, GlobalFoundries set up a DSA R&D line at Albany Nanotech. Using a chemical epitaxy flow, the company also demonstrated a three-stack, 28nm silicon fin structure.

There are two types of DSA flows—graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide structure is spin-coated, rinsed and spin-coated again with copolymers using a track system. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographic-determined chemical patterns.

In DSA, there are two types of defects–topological and buried. Topological defects tend to be at the top of the structure and are relatively easy to find. The industry has found a way to reduce those types of defects by tweaking the process flow. “The buried defects, on the other hand, are very troublesome,” said GlobalFoundries’ Preil. “These defects clearly cluster on the lines that have a neutral layer underneath them. We refer to these defects as peapods, because they really look like peas lined up in a pod.”

Buried defects are difficult to eradicate. Then, GlobalFoundries and AZ Electronic Materials made what could be a major breakthrough. Researchers changed the neutrality of the underlying neutral layer in the material. “AZ changed the neutral layer to be more neutral. The defects practically went away. It went from a factor of a thousand defects to four. And the defects didn’t have the repeating nature of the peapod,” he said.

Researchers also found the root of the original problem. “What happens is the PMMA sucks itself down to the bottom layer a little harder than it should. And that displaces the polystyrene, which then has no place to go but up and over and form these peapod bridges,” he said.

GlobalFoundries also laid some groundwork for the next-generation high chi materials, which will scale beyond 12.5nm. “The cylindrical block copolymers have received a lot of attention,” Preil said. “The benefits of using these materials are lower interfacial roughness and higher etch contrasts. They have intrinsically lower defect levels. Now, the downside is that there is an etch integration problem. Taking a round cylinder and turning into rectangular etch is a challenge. If you want lamella structures, that can be done. But that’s still a lot less mature.”

On the high chi front, GlobalFoundries made some progress using two so-called hard graphoepitaxy flows. “One (flow) was called litho-etch DSA, where we opened up the ARC pattern and then we put down the DSA materials. So the anti-reflection coating acts as the guide. We got nice pitch triplication,” he said. “The other process is called SADP DSA, where we did a conventional sidewall deposition. And then, we used the sidewall pattern to confine the DSA.”

Meanwhile, in another breakthrough, TEL demonstrated the ability to handle the pattern transfer process with tight specifications, thereby bringing DSA-enabled chips one step closer to reality.

Using today’s PS-b-PMMA materials, TEL used AZ Electronic Materials’ process flow in order to transfer a pattern from a tri-layer stack. In the initial etch step, TEL saw a line-edge roughness (LER) of 2.2nm. After the transfer process, TEL ended up with an LER of 1.5nm. “This 1.5nm number is the target for these features in manufacturing,” said Mark Somervell, senior lithography technologist at TEL.

Still to be seen, however, is just how the design community will embrace DSA. “In the first applications for DSA, you might have restrictive designs,” said Aki Fujimura, chairman and chief executive of D2S.

All told, DSA remains a promising technology, but it won’t be all things for all people in designs. “I see DSA succeeding,” Fujimura said. “But it’s not going to be used by everybody for everything. It will mainly be used for a specific target.”