ECTC Packaging Trends

At the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas, a number of packaging houses, R&D organizations and universities presented a slew of papers on the latest IC packaging technologies.

The event provided a glimpse of the future of packaging, which is becoming more important in the industry. At one time, IC packaging took a backseat in the semiconductor industry. The package was simply there to house a chip at the lowest possible cost.

Now, IC packaging is playing a bigger role in the industry as traditional chip scaling is slowing. And the industry is looking for new solutions. 2.5D/3D, chiplets and fan-out are among the options. “You have all of these different architectures across the board to achieve many of the same things. You need higher performance at a lower cost,” said Kim Arnold, executive director for wafer level packaging materials at Brewer Science.

Each packaging technology is different and belongs in a different category or bucket. By categorizing them, it becomes easier to understand where they fit. “If you put them in buckets, you can start to look at the requirements, what’s unique about what vendors are trying to achieve, and what kind of markets they are pursuing,” Arnold said in an interview at ECTC.

At ECTC, the industry talked about these and other packages, not to mention other technologies. It’s difficult to write about all of the papers at ECTC, but here’s a link to some presentations. Here is a link to more papers.

Here’s a link to the program and papers (at least the titles) presented at ECTC. At the event, there were also several panels and sessions. In chronological order, here’s some of the events:

Packaging roadmaps
The first big event at ECTC was the Heterogeneous Integration Roadmap Workshop. At the day-long event, the technical working groups celebrated the completion of the first edition of the IEEE EPS Heterogeneous Integration Roadmap.

Members of each technical working group also presented details about the roadmap. In simple terms, the Heterogeneous Integration Roadmap addresses the packaging, test and interconnect technologies required for the next 15 years.

Generally, the overall idea behind heterogeneous integration is to integrate multiple die in the same package. This enables the package to perform a specific and advanced function in a small form factor. Heterogeneous integration has other implications—it is becoming an alternative to IC scaling. Packing more transistors on a monolithic IC is becoming more difficult and expensive at each node. Another way to get the benefits of scaling is by putting multiple and advanced chips in an IC package.

Meanwhile, the origins of the Heterogeneous Integration Roadmap started in 2015, when the Semiconductor Industry Association (SIA) announced that it would bring the old International Technology Roadmap for Semiconductors (ITRS) activities to a close. For years, the ITRS served as the roadmap for the IC industry.

At the time, a working group within the ITRS believed it was important to continue the work with a roadmap dealing with heterogeneous integration. By the end of 2017, there were 17 different technical working groups within the new Heterogeneous Integration Roadmap.

In 2019, there are 21 working groups in five areas, such as market applications, heterogeneous integration components, design, cross cutting topics, and integration processes. The idea behind the roadmap is clear. “The objective is to find a mechanism that we can use like the same thing we did in the ITRS. We take the collective knowledge in the world and integrate it together. We identify the roadblocks that are going to stop us and we do it early enough in advance. What we want to do is to stimulate pre-competitive collaboration,” said Bill Bottoms, co-chair of the Heterogeneous Integration Roadmap committee, who moderated the workshop at ECTC. Bottoms is also chairman of Third Millennium Test Solutions.

This roadmap serves as a guide for companies. Each company can follow the roadmap or take its own path.

At the event, meanwhile, a member of each technical group presented details and the challenges within a given area. In the near term, the committee plans to make the details of each area public. Here’s a link for more information.

Brain-in-a-package and dielets
The next event was a panel discussion, entitled “Future (Visions) of Electronic Packaging.” At the event, there were several presentations. In one, Georgia Institute of Technology discussed a technology called “brain-in-a-package” using dielets.

Dielets are a similar concept to chiplets, which is a way of integrating multiple dies in a package or system. The basic idea is that you have a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme.

Georgia Tech proposes to use the dielet concept to house neuromorphic chips. In neuromorphic computing, the goal is to replicate the brain in silicon using an advanced neural network.

For these chips, the industry would generally use a 2.5D package. Instead of a traditional package, Georgia Tech has a different approach. “We looked at something which combines the benefits of a 2.5D-type architecture as well as a 3D-type architecture. We come to something which looks like a 2.5D on top of another 2.5D,” said Shreya Dwarakanath, a graduate research assistant at Georgia Tech. “What we see is basically dielets embedded in a mold compound that are fanned out and assembled onto an active interposer. These dielets could be either CMOS or non-CMOS and be neuromorphic computing based.”

Clearly, chiplets are generating a buzz in packaging. Watch out for dielets too.

Biotech
Then, in a separate keynote address at ECTC, John Rogers, a professor of materials science and engineering at Northwestern University, presented the latest results in the field of biotechnology.

For some time, Rogers and his associates have been developing soft materials, such as polymers, liquid crystals and others. The goal is to leverage these and other materials to develop bio-inspired nanophotonic structures, microfluidic devices and microelectromechanical systems.

In one example, Northwestern presented its latest results in the journal APL Materials. In the paper, Northwestern has developed flexible bioelectronic implants, which can be used for diagnostic functions in various applications in humans.

Northwestern is also working on biodegradable electronics and other technologies. “Ultimately, for any of those areas, you would like to leverage the very best of what’s available in standard, well-established electronics materials, circuit designs and processing approaches,” Rogers said during the keynote. “The problem statement then becomes taking a wafer on CMOS and converting it into this biocompatible type of form.”

Rogers and his group have posted their research papers here.

Packaging for autonomous cars
Not to be outdone, ECTC held another panel, entitled: “Sensors and Packaging for Autonomous Driving.”

Clearly, the next big things are self-driving cars and advanced driver-assistance system (ADAS) technologies. Self-driving cars are still in R&D, but ADAS is already here. ADAS involves various safety features in a car, such as automatic emergency braking, lane detection and rear object warning.

In the ADAS world, “Level 1” involves the automation of one or more control functions in a car, while “Level 2” is the automation of two or more functions. “Level 3 and 4” involve more self-driving capabilities. “Level 5” is fully autonomous, steering-wheel optional.

Today, the most advanced cars are Level 2. Level 4/5 are still way in the future and will require more technical breakthroughs. “In order to do all of this, full-automation will require equipping the car with significantly greater computing power and memory capacity,” said Tu-Anh Tran of NXP, during the panel.

It also requires more advanced packaging. But still, the requirements for automotive are stringent and OEMs will continue to use the older packages. “Automotive is still very conservative, so most of the packaging is mature. Even SOICs are still running in volumes. QFP and BGA are also used,” said Scott Chen, senior vice president of central development engineering at ASE, during the panel.

Still, for the compute and other functions in the car, the automotive industry is moving towards more advanced 2.5D and fan-out packages. For example, fan-out is used to package the radar modules in some vehicles. In some cases, 2.5D is being used for the compute system in the car. “These are already involved in the new devices, because we need high-performance computing,” Chen said.

There were more events and papers at the ECTC. It’s hard to see them all. Hopefully, I will attend more at ECTC in 2020 in Orlando, Fl.