Are current methodologies sufficient for ensuring that chips will function as expected throughout their expected lifetimes?
Andre Lange, group manager for quality and reliability at Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks about circuit aging, whether current methods of predicting reliability are accurate for chips developed at advanced process nodes, and where additional research is needed.
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Thanks Ed and Andre for keeping reliability challenges in the forefront. For 18-year life, I would think that performance margin (added design margin in timing closure, redundant metal routing, etc.), as well as test margin (requiring voltage and performance margin in excess of use conditions to account for aging (and accepting the yield trade-off) would be necessary.