How Many Nanometers?

What’s the difference between a 10nm and a 7nm chip?

That should be a straightforward question. Math, after all, is the only pure science. But as it turns out, the answer is hardly science—even if it is all about numbers.

Put in perspective, at 65nm, companies defined the process node by the half pitch of the first metal layer. At 40/45nm, with the cost and difficulty of developing new process technology creeping up, and more expensive and complex equipment required to manufacture chips, the competitive stakes began skyrocketing. While these distinctions didn’t mean much to the end markets buying those chips, a difference of 5nm did make it harder to second-source designs at a competitive foundry. By altering line widths, IP that was characterized for one process didn’t necessarily behave the same way using a different process.

This competitive split continued at 32/28nm, as well. But at 20nm, confusion was added to that competitiveness. Despite the fact that two of the highest-volume mobile phone SoCs were developed at 20nm, most other chipmakers viewed 20nm as a bad investment. Leakage current was higher than at 28nm, and 20nm required double patterning because immersion lithography using a 193nm ArF laser reached its limit at 22nm. After that, EUV lithography was supposed to take over because it has a diameter of only 13.5nm. But as the semiconductor world well knows, EUV has taken far longer than anyone ever anticipated.

Rather than throw away their investment in 20nm process technology, commercial foundries added 16nm (TSMC, and now SMIC) and 14nm (GlobalFoundries, Samsung, and now UMC) finFETs onto a 20nm back-end-of-line process. Are those chips 16/14nm, or 20nm? It depends which side of the egg you’re looking at. Intel, meanwhile, has moved from 22nm finFETs, which it developed without double patterning, to 14nm finFETs, using a 14nm BEOL process and 14nm finFETs.

It gets worse from there. The push to 10nm and 7nm offers the same confusing array of back end of line, front end of line, with a new middle of line piece. But because these are all well beyond the capabilities of immersion lithography to etch a chip on a single pass, there are now between 80 and 120 masks required, each slightly different. So 7nm could be 7.3nm, or it could be 6.8nm.

This has become so confusing, in fact, that these comparisons are now almost meaningless. They do signify a progression from one process to the next, almost like the shift from Windows 7 and 8 to Windows 10. And it doesn’t really matter that Microsoft skipped Windows 9. You generally want the latest release. In the case of software, it’s the higher number. In the case of manufacturing processes, it’s the lower number.

But the reality is that you can’t compare a 7nm chip from one foundry to a 7nm chip from another foundry anymore. Even foundry processes aren’t comparable. IP developers complain that version 1.0 of the process isn’t as robust as version 1.0 at a pre-finFET node.

Chipmakers still choose process technology based on the best price or service guarantees or IP availability or fastest time to silicon with guaranteed capacity. And process terminology may be less important, particularly as the industry begins adopting heterogeneous advanced packaging techniques. But it still does matter. It’s a reference point in a highly confusing industry.

Still, those reference points need to be adjusted and tweaked like the processes they define. And all of that needs to be done by an industry standards group that can establish an array of definitions. So why is the industry so quiet on this subject?

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