How To Build Systems In Package

The semiconductor industry is racing to define a series of road maps for semiconductors to succeed the one created by the ITRS, which will no longer be updated, including a brand new one focused on heterogeneous integration.

The latest entry will establish technology targets for integration of heterogeneous multi-die devices and systems. It has the support of IEEE’s Components, Packaging and Manufacturing Technology Society (CPMT), and is sponsored by SEMI and the IEEE Electron Devices Society (EDS). Along with the IRDS road map, it marks yet another facet of the overall semiconductor industry’s shift away from just shrinking features sizes. Rather than pushing everyone to advanced process nodes, which are complex and expensive to develop, solutions are being developed that address specific market needs.

Those solutions involved many different components and technologies, and advanced packaging is considered an enabler for the kind of heterogeneous integration that is required. One of the selling points of this approach is that it can speed time to market by integrating off-the-shelf IP and components developed at different process nodes. It also can boost throughput and reduce power, which so far have been the main drivers for 2.5D chips.

Establishing a flow
The process begins with chip-package-system co-design and performance and thermo-mechanical simulation. That, in turn, is followed by assembly of those devices and passives into a system-in-package (SiP). From there, the whole system needs to be effectively tested. The problem is that there are too many options for doing this work, too little data available about what works best, and far too little guidance to achieve consistent yield and generate economies of scale. That’s why there is so much buzz around these new road maps.

“The ITRS road map took on a life of its own, and for many of our members, it was the only road map,” said Tom Salmon, vice president of collaborative technology platforms at SEMI. “Some time back, the ITRS became less referenced as a guideline as it tried to reinvent itself with an application focus. Now, there are a number of different groups moving forward with different road-mapping activities.”

Last fall, the Semiconductor Industry Association said it would end ITRS activities in spring 2016, so the upcoming publication of the 2015 edition will be the final edition. From the outside, a number of road maps tied to more specific market applications may seem like a sudden shift, but in some respects this is less abrupt than it might seem. CPMT, for example, has had a long association with the ITRS Assembly & Packaging Technical Working Group and the Heterogeneous Integration Focus team. The Heterogeneous Integration Road Map is more like an evolution of that relationship for the IoT/IoE/cloud computing era rather than a break from the past. It will continue to focus on pre-competitive technology, with a recognition that not all semiconductors will be architected and packaged using exactly the same approach that drove Moore’s Law for a half century.

Already shipping
Huawei, IBM, AMD, and Intel are all shipping 2.5D-based solutions for their products, and eSilicon has reported an uptick in 2.5D designs. But collecting best practices and guidelines for these kinds of packages is essential to developing the library of data necessary to push this approach into the mainstream to achieve economies of scale.

“With packaging, different parts of the package need different things,” said William Chen, a fellow at Advanced Semiconductor Engineering (ASE). “Some applications, whether that is 2.5D and fan-out, will require new tools. For others, like 5G, the front-end portion will require a different kind of co-design (chip-package-system) to optimize very high frequency requirements. Our technical community doesn’t have one kind of tool for this.”

The road map will be developed by a number of technical working groups (TWGs), which will outline assembly, packaging, test and interconnect technologies that will be required over the next 15 years, with a 25-year outlook for emerging research areas. Included in the road map will be silicon photonics, power input and voltage control, as well as best practices for heat dissipation, consideration for new materials and device types, including bio-chips and MEMS, and 3D-IC architectures.

“As an industry, we are moving toward a predominance of multi-die devices, from integrated circuits to integrated subsystems and system-in-package (SiP),” said Chen. “In light of this, it is critical that we have a road map that recognizes end-market inflection points and system-level implications, as well as identifies technologies at both semiconductor and package integration levels to address emerging needs.”

The focus of this group is more far reaching than the name implies. “This is not just about the package,” SEMI’s Salmon pointed out. “This is about optimizing integration at the die, package and system level. IEEE CPMT and EDS (Electron Devices Society) and SEMI are the natural place to start. We are open to collaboration with other organizations and other roadmaps wherever possible.”

The initial road map committee will include Chen, Salmon, IEEE’s Bill Bottoms, and Subramaniam Iyer, UCLA professor and IEEE EDS fellow. Working group members so far include Intel, IBM, Cisco, X-Celeprint, Fraunhofer Institute, the universities of Greenwich (U.K.), Maryland, Texas, Georgia Tech, Osaka University and North Carolina State University and others.

The first HITRS road map workshop was held at the ECTC Conference in Las Vegas on May 31. Presentations focused on the purpose, governance and organization of the HITRS road map. A proposed list of technical working groups (TWGs) was reviewed. The next meeting will be an all-day workshop on July 10, followed by a half-day meeting at Semicon West on July 11. That meeting will be followed by a series of workshops throughout Asia, Europe and North America. The goal is to complete the 2016 HITRS road map by next spring.

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