Inside Leti’s Litho Lab

Directed self-assembly and multi-beam take on new importance as the future of EUV lithography remains in limbo.

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By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Serge Tedesco, lithography program manager at CEA-Leti; Laurent Pain, lithography lab manager at CEA-Leti; and Raluca Tiron, a senior scientist at CEA-Leti.

SMD: CEA-Leti has two major and separate programs, including one in directed self-assembly (DSA) and another in multi-beam e-beam. Let’s start with DSA. What is CEA-Leti doing in DSA?
Pain: For DSA, we have what we call the ‘Ideal’ program. We are developing 300mm processes. We have materials development with Arkema. Other partners include TEL and Sokudo. We are working with STMicroelectronics to transfer the technology from a process point of view. We are developing this capability for lab scaling to industry production.

SMD: What have you demonstrated with DSA?
Pain: We have demonstrated resolutions down to 18nm half-pitch, which is considered the 7nm logic node. We think we can extend PS-b-PMMA down to the 7nm node. The concept is to enable 7nm to 4nm resolutions with Arkema’s materials.

SMD: The big question is when do you think DSA will move into production?
Pain: From my point of view, it should be 10nm. You will start to see some demonstrations at 14nm.
Tedesco: You can ask me that in July. I still say 2014.

SMD: What are the challenges with DSA?
Pain: There will be some challenges in terms of defectivity and process maturity.
Tiron: For contact shrinks, the processes are here. It’s stable. That means you can absorb a lot of the variations with the block copolymers. But you don’t have pitch or density. If you move to contact doubling, you have the density. But you lose the process window stability. The placement of the contacts is also less certain. But what is important is now we have materials, processes and tracks. What we really need now is some real fabrication. The applications depend on the end-user. What we need is the end-users to tell us: ‘We need this and that and then move in that direction.’ That’s what is missing today.

SMD: What have you accomplished in your DSA process flow?
Tiron: We have implemented a process flow on a 300mm track, which comes from Sokudo. We have a complete DSA process cycle in one track. The track handles the brush coat and block copolymer coating. The track also has high temperature hot plates for block copolymer cure. We also worked with Sokudo to develop a PMMA removal process. We demonstrated different exposure treatments and solvents. What we are trying to do now is address contact hole shrinks and contact multiplication. With the polymers from Arkema, we are able to do resolutions from 20nm period, which means 10nm resolution, to 60nm period, which means 35nm resolution. Contact shrink is possible using both cylindrical and lamellar morphologies.

SMD: What about yield or defects?
Tiron: We have shown good uniformities with three sigma around 2nm. After the optimization of the process, we counted 6,800 divisional points on the wafer. We only found five missing contacts. By using block copolymers, we showed 99.93 % valid contacts on the wafer. This is just using PMMA.

SMD: Let’s move to multi-beam. What is CEA-Leti doing in multi-beam?
Pain: The second program is called Imagine. This program started last year. We have a partnership with (multi-beam e-beam vendor) Mapper Lithography. Other partners include Aselta, JSR, TOK, TSMC, Sokudo, Dow, STMicroelectronics, TEL and Mentor.

SMD: How far along is Mapper’s multi-beam tool?
Pain: The first machine will consist of 1,300 beams. The throughput is one wafer per hour. The tool will arrive the beginning of June. That’s targeted for the 14nm logic node. This machine will be interfaced with the Sokudo track. The first exposures will start in the last quarter of this year. Eventually, the target is to reach 16nm half-pitch. Our goal is to have 13,000 beams with the Mapper tool. We expect to scale the throughput from one wafer per hour to 10 wafers an hour. Then, we plan to push the resolutions down to 10nm half-pitch.

SMD: What is the cost-of-ownership for the Mapper tool?
Pain: The cost is 1 million euros for two wafers per hour. So in other words, that’s 5 million euros for 10 wafers per hour. Our eventual goal is to cluster 10 machines together. That’s 50 million euros for the cluster configuration.

SMD: Isn’t multi-beam taking longer than expected and behind schedule?
Pain: If you take the original roadmap, we are late. Some of the technical achievements have taken a long time.
Tedesco: One of the problems is there is a lack of support from the industry. It’s a shame that there is a lack of support, when you look at what’s being done on the EUV side. That’s one of the reasons that multi-beam is not mature yet. Of course, there is the technical aspect. TSMC, of course, is the one that is pushing this technology. But beyond TSMC, there is a lack of support. But I think the support will eventually come.

SMD: TSMC has stated it wants to do all layers with multi-beam. Is that practical or will multi-beam end up doing traditional direct-write applications like ASICs?
Tedesco: It could be a challenge to do all layers with multi-beam. But a maskless tool could be useful in terms of ASICs or prototyping. It’s ideal for the foundries. But the first applications for multi-beam will likely be contact holes and the cut layer.

SMD: How about STMicroelectronics? STMicroelectronics has been involved with direct-write for many years.
Tedesco: ST is a partner of Leti. So they are following Imagine very closely.

SMD: What about funding for multi-beam from the likes of Intel, GlobalFoundries and Samsung?
Tedesco: Good question. What we can say is that they are following us very closely. They know what we are doing. At this point, they are not part of the program.