Interconnects Approach Tipping Point

As leading devices move to next generation nanosheets for logic, their interconnections are getting squeezed past the point where they can deliver low resistance pathways. The 1nm (10Å) node will have 20nm pitch and larger metal lines, but the interconnect stack already consumes a third of device power and accounts for 75% of the chip’s RC delay.

Changing this dynamic requires a superior conductor, particularly at 18nm metal pitch, to better transfer signals and power efficiently. So even though copper-based solutions are being extended to the limit in fabs, the industry is preparing for the tipping point from copper to an alternative metal.

A likely solution involves replacing copper with ruthenium (Ru) interconnects at the lowest, tightest levels, perhaps as soon as the 14 Å node. And, though it is possible to stay with the existing damascene-based processing, a change to subtractive schemes is more than likely because it enables a more flexible, scalable path to connecting taller CFET devices and beyond.

At the same time, some memory device makers are evaluating an interconnect change of their own. Tungsten interconnects, used in DRAM and 3D NAND, may be nearing their limit of extendibility, though the need for an alternative appears to be less imminent. Tungsten is used to form word lines in DRAM, contacts and plugs in 3D NAND, and contacts in logic. Molybdenum (Mo, aka moly), is tungsten’s likely successor. These choices follow years of evaluating chemical properties in thin films and features, as well as testing using various processes and flows including damascene’s dielectric etch and metal gap fills versus subtractive etch and dielectric gap fills.

“There are a number of factors to consider in the selection of a metal, and resistivity is among the most important,” said Kaihan Ashtiani, corporate vice president and general manager for ALD/CVD metals at Lam Research. “At the atomic dimensions required for advanced chipmaking, moly is emerging as the most suitable material to replace tungsten, creating a major inflection point in the industry.”

In addition to low resistance at nanometer dimensions, molybdenum does not require a high resistivity barrier to achieve the best device properties, whereas tungsten typically does. “Because moly has little to no intrinsic diffusivity into dielectric materials, it does not require a barrier liner,” said Ashtiani.

In a similar manner, ruthenium does not need a barrier metal, so the majority of the available interconnect volume can provide a continuous, low resistance path for device current to flow.

Engineers and researchers are preparing for both transitions, but neither will occur overnight. “Everything [in logic] today is copper, single damascene or dual damascene, including all the tools installed in the foundries,” said Zsolt Tokei, imec fellow. “So if something is going to be changed there, it can only be gradual. And that’s why we were trying to think about a step-by-step implementation.”

Making ruthenium and molybdenum work
After copper’s 30-year reign, ruthenium appears to be the furthest along in terms of demonstrating manufacturability and reliability. It can be deposited by several means, including sputtering (physical vapor deposition, or PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or electroless plating.

Companies such as TSMC, Intel, IBM Research and Samsung are working on integration schemes for ruthenium-based interconnects. To drive down capacitance, and therefore RC delay, all leading logic fabs have evaluated the benefits of ruthenium integrated with air gaps (dielectric constant k = 1.0) on a single layer, with substantial benefits.

Fig. 1: Tightly packed local interconnections have the finest features while global interconnects are delayed less by RC. Source: Lam Research

Unfortunately, a significant drawback to incorporating air gaps into devices is reduced mechanical stability. For this reason, it would likely be used on alternating layers and sparingly, especially in the first generation where established low-k gap fill dielectrics would likely be integrated with ruthenium initially.

Because ruthenium does not require a barrier layer, it can be directly etched. It also does not oxidize easily, and it has a shorter electron mean free path to limit scattering’s effect on resistance at short linewidths. The switch to subtractive etch is at least partially motivated by problems such as line wiggling and twisting at tight dimensions. Other benefits of deposition-etch schemes include less variation in line height (better control with etch than CMP) and the possibility of fabricating lines at higher aspect ratios than 2:1, the approximate limit with damascene structures. Higher aspect ratio lines will be more compatible with the upcoming CFET structures.

Studies are still underway to fully understand ruthenium’s electrical behavior in tight features. Some of the metrics that most influence metal resistance include grain size, the electron mean free path, and the average reflection coefficient at grain boundaries. “First principles simulations may play a key role in understanding the mechanisms behind the resistance increases, and aid in the search for replacement materials,” said Troels Markussen, Synopsys, lead author of a study co-published with IBM Research. [1]

Imec’s process flow called semi-damascene is a two-layer module that potentially can be extended to multi-layer stacks. [2] “We see extending copper to about 20 nanometers, and very clearly we propose direct metal etch for 18 nanometer pitch and below, for several reasons,” said imec’s Tokei. He explained that ruthenium is cleanly deposited and etched using existing process tools. Furthermore, for advanced logic, it is not just the initial layers that benefit from the metal replacement. “Our data show that the stacked via resistance is very important all the way up to M5.”

There are several process integration challenges to making semi-damascene work, and Tokei emphasized that only the chipmakers can prove the reliability of ruthenium implementation in high-volume manufacturing. “We can say that for semi-damascene, yes, the approach needs to be fully self-aligned. Yes, your via-to-line leakage needs to be in spec. Yes, your DPPM needs to be correct, and the metal needs to be air-gap compatible. And yes, it needs to pass electromigration and other reliability testing. On top of that, it needs to be implementable in your fab.”

Such a long list of requirements will take time to meet, but the progress to date still indicates this is a path logic makers eventually will tread.

The promise of molybdenum
These are early days for molybdenum interconnects, but there is a great deal of activity behind the scenes. “Nearly all major chipmakers are in various stages of qualification (of molybdenum) in their NAND, DRAM and logic applications,” said Lam’s Ashtiani.

In addition to compatibility with existing damascene-based flows and no need for a barrier layer, another significant advantage is molybdenum’s low cost. And process tools are progressing. For instance, molybdenum can be deposited using ion beam deposition (sputtering) at 400°C to achieve even lower resistivity than tungsten, and the grain structure can be optimized, which highly depends on the film substrate. [3]

Extending copper and tungsten
Chipmakers only change out materials when there is no other choice. Until then, they are continuing to make small modifications to existing interconnect flows to eke out better PPA from copper- and tungsten-based interconnects.

Fig. 2: Roadmap for semi-damascene with ruthenium and air gaps. Source: imec

In dual damascene flows, copper is deposited into trenches and valleys previously etched in a dielectric insulator in a scheme called dual damascene process, first filling the via and then the line. One of the reasons copper is so difficult to extend to tiny pitches is the bulky barrier, liner and cap layers that keep it from diffusing into adjacent regions and prepare the features for smooth gap fill by electroplating. These additional layers consume very valuable conductor volume, and the metals have higher resistivity than copper, which elevates the overall resistance. What it comes down to is a 10nm wide line may only include around 4nm- to 5nm-wide copper once the TaN barrier layer, cobalt liner, and cobalt cap are deposited.

Some of the changes that extend copper damascene interconnects use lower-resistance via processes, thinner TaN diffusion barriers by atomic layer deposition (rather than PVD), alternative liners such as ruthenium-cobalt (Ru-Co), and elimination of the barrier layer at the bottom of vias. Engineers also find that by implementing self-aligned or fully aligned vias (top and bottom alignment), they can drive down edge placement errors between lines and vias, improving performance and potentially preventing leakage and reliability failures.

Deposition tools are also having a harder time filling tiny gaps by electroplating without defects or voiding. Some approaches target the liner metal, typically cobalt, which acts as an adhesion layer between the TaN barrier and copper. For instance, as interconnect pitches approach 20nm, thinning the cobalt liner can lead to poor copper wettability and reliability failures.

One alternative replaces Co with a bilayer of ruthenium and cobalt (Ru-Co). Samsung reported on the optimization of a Ru-Co liner to improve copper gap fill at the 3nm node. “There is a growing recognition of the necessity for improvements in liner processes and film properties that can directly influence copper filling ability,” noted Hehsang Ahn and colleagues at Samsung Electronics. [4] The Ru-Co bilayer can be deposited using one or two CVD chambers, with intermittent plasma processes to reduce film roughness for more effective plating. Samsung’s reliability studies of these TaN/Ru-Co/Cu interconnects indicated that Ru-Co can produce a thinner liner with superior wettability than cobalt alone, with 87% fewer voids and 14% better line resistance at tight dimensions. [5]

Many companies have eliminated or are working to eliminate the TaN barrier layer at the bottom of vias (landing on copper lines), because it can account for up to 60% of via resistance. Self-assembled monolayers, either spin-on or deposited films, can be used to prevent barrier deposition on the via bottom while still allowing deposition of the barrier metal on the via sidewalls, known as selective deposition. This represents a key strategy in stalling the transition to a next-generation metal.

At the same time, any transition must be based on specific device requirements. “Another question is how important is your resistance? It may not be that critical immediately, but it becomes a system question at some point. Even at an aspect ratio of 2 you already have better resistance with direct metal etch than copper,” said imec’s Tokei. “If it were available today, it would be a no-brainer, but this is a disruptive change. In fact, our data shows that even at 36nm pitches, the performance with ruthenium is slightly better. But you don’t take just a slightly better process and implement it.”

And factors beyond RC are influencing architectural and material changes, including device heating and reliability.

Heat spreading from switching transistors
A key concern with BEOL interconnects is the scaling-induced temperature rise. The stack has low thermal resistance, so the interconnect region heats up. This is mostly caused by transistor switching, which can induce reliability failures due to electromigration and stress migration. The temperature increases can affect transistor reliability, as well, in the form of time-dependent dielectric breakdown (TDDB).

Another phenomena called Joule heating is caused by high currents running through copper carrying signals and power. As the industry transitions from silicon dioxide (k = 4.0) inter-level dielectric to low-k films (3.3 or lower) to perhaps air gaps, this warming trend will only become exacerbated because these materials involved are less and less thermally conductive.

These thermal concerns used to be confined to primarily the first level of metal, but increasingly, engineers find this assumption no longer holds for leading-edge processors and accelerator chips.

Backside power distribution
Another disruptive change in the way interconnects are fabricated involves backside power delivery (BPD), which moves power delivery to the wafer backside so that interconnecting levels above the transistors only carry signals. This change can enable a one-time relaxation of metal pitch on the frontside of the wafer, while potentially delaying the introduction of ruthenium for perhaps a device node.

The reason to split power from signal lines is because the two forms of transmission have different needs. Power ultimately benefits from a low resistance path (fatter wires), but large currents make it susceptible to electromigration. For signals, small cross-sections work because they need low capacitance, but some resistance is okay. With 15 metal levels or more in advanced logic, there’s a rise in power density and voltage drop (IR drop) that is significantly limiting performance. This is one of the reasons why process and material changes must be viewed from a holistic perspective.

Conclusion
The changes from damascene-based flows to subtractive deposition-etch flows, combined with a change from copper to ruthenium, represents a massive, disruptive change in interconnect processes for logic manufacturers. Each advance in new liner metals, atomic layer deposition, and etching brings the alternative metallization scheme closer to a manufacturing reality.

Likewise, processing to enable molybdenum interconnects in DRAM and 3D NAND are moving quickly, seeking the best material and equipment combination to realizing low resistance, reliable interconnections.

In the semiconductor industry, material and architectural changes only happen when existing flows absolutely cannot meet performance specifications. Nevertheless, fabs will continue to extend copper and tungsten flows beyond exiting capabilities. With a huge investment in tooling, materials, and recipes for copper dual-damascene and tungsten metallization, any metal replacement likely will take place in a gradual step-wise fashion.

References

1. T. Markussen et al., “Grain boundary scattering in Ru and Cu interconnects,” 2020 IEEE International Interconnect Technology Conference (IITC), San Jose, CA, USA, 2020, pp. 76-78, doi: 10.1109/IITC47697.2020.9515604.
2. Z. Tokei, “Semi-damascene metallization: inflection point in back-end-of-line processing?” imec-int.com, Oct. 31, 2024, https://www.imec-int.com/en/articles/semi-damascene-metallization-inflection-point-back-end-line-processing.
3. R. J. Mehta et al., “Ion Beam Deposition of Low-Resistivity Tungsten and Molybdenum for Interconnect Applications,” 2024 IEEE International Interconnect Technology Conference (IITC), San Jose, CA, USA, 2024, pp. 1-7, doi: 10.1109/IITC61274.2024.10732475.
4. H. Ahn et al., “Improvement of Ru-Co Liner for void-free Cu interconnect in extremely small pitch,” 2024 IEEE International Interconnect Technology Conference (IITC), San Jose, CA, USA, 2024, pp. 1-3, doi: 10.1109/IITC61274.2024.10732520.
5. G. Myeong et al., “Highly Reliable Ruthenium-Cobalt Binary Liner for Advanced Node Cu Interconnect,” 2024 IEEE International Interconnect Technology Conference (IITC), San Jose, CA, USA, 2024, pp. 1-3, doi: 10.1109/IITC61274.2024.10732516.

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