Manufacturing Bits: Dec. 17

Implantable TFETs
At the recent IEEE International Electron Devices Meeting (IEDM) in Washington, D.C., a number of companies, R&D organizations and universities described new breakthroughs in perhaps the next big thing in semiconductors–the tunnel field-effect transistor (TFET). Aimed for the 5nm node, TFETs are steep sub-threshold slope transistors that can scale the supply voltages below 1 volt, and possibly as low as sub-0.5 volts.

In one paper at IEDM, Pennsylvania State University, the National Institute of Standards and Technology (NIST) and IQE described a near broken-gap TFET. The chip is geared for medical devices, which can be implanted inside the human body.

The energy barrier is close to zero–or near broken gap. This allows electrons to tunnel through the barrier when desired. Researchers also moved the contacts to the same plane at the top surface of the vertical transistor. The TFET is based on III-V channel materials using an InGaAs/GaAsSb system. The near broken-gap TFETs with 200nm channel lengths exhibit record drive current (ION) of 740μA/μm, intrinsic RF transconductance of 700μS/μm, and a cut-off frequency of 19GHz at VDS=0.5V.

Transmission electron microscope cross-section of the vertical TFET. (Source: Suman Datta/Penn State)

“This transistor has previously been developed in our lab to replace MOSFET transistors for logic applications and to address power issues,” said Penn State graduate student Bijesh Rajamohanan, on the university’s Web site. “In this work, we went a step beyond and showed the capability of operating at high frequency, which is handy for applications where power concerns are critical, such as processing and transmitting information from devices implanted inside the human body.”

In another significant IEDM paper, Intel rolled out the resonant-TFET (R-TFET). The device has a steep sub-threshold slope of about 25mV/dec over around 3.5 decades of current. This enables the scaling of the tunneling transistors to sub-9nm gate-lengths.

The R-TFET uses the same material combination as Intel’s double-gate heterojunction TFET, but in reverse order. “Thus, the material with the low conduction-band edge is in the N-TFET source region. This band order creates a narrow triangular potential well at the source side of heterojunction, with discrete resonant energy levels. In the semi-classic view, this design increases the effective bandgap for tunneling, making it a low drive-current TFET,” according to Intel researchers Uygar Avci and Ian Young.

“If the resonant energy levels align with the source valance band only when the device is on, this enables a faster change in tunneling rate between on and off regions. The resulting R-TFET therefore has significantly steeper (sub-threshold slope) than a heterojunction TFET,” they added.

Self-assembled ReRAMs
Resistive RAM (ReRAM) is being touted as a futuristic replacement for today’s flash memory. ReRAM is attractive because it is said to deliver faster write times with more endurance than today’s flash.

At IEDM, there were a plethora of ReRAM papers. One paper from Stanford described a metal-oxide ReRAM device, which was fabricated using a diblock copolymer self-assembly process.

This patterning technique enabled researchers to scale down the memory device to less than 12nm. The fabricated bi-layer TiOx/HfOx device demonstrated forming voltages of about 2.5 Volt and low switching voltages of 1E7 cycles). Furthermore, the device has a switching speed of about 50ns.

ReRAM device fabricated with DSA (Source: Stanford)

In Stanford’s self-assembly process, a diblock copolymer, PS-b-PMMA, is dissolved in propylene glycol methyl ether acetate. Then, the solution is spin-coated to 30nm to 40nm thick on the substrate. The sample is annealed at 185 degrees C for 12 hours under a nitrogen environment to facilitate the self-assembly process, according to Stanford.

Then, the sample is exposed under deep ultra-violent (DUV) light for 10 minutes and immersed in glacier acetic acid for 20 minutes. By selectively removing the PMMA component, a PS template of close-packed array of holes with about 20nm diameter is obtained and this PS template then serves as a soft-mask for etching, according to Stanford. “Diblock copolymer self-assembly could produce nanoscale chips more efficiently and less expensively than the lithography techniques in use today,” said H.-S. Philip Wong, a professor of electrical engineering at Stanford, on the university’s Web site.

FinFETs vs. FDSOI
Outside of Intel, leading-edge chipmakers are looking at various options beyond the 20nm logic node. At the 16nm/14nm node, chipmakers have at least two viable options–finFETs and planar transistors based on fully-depleted silicon-on-insulator (FDSOI) technology.

At IEDM, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) presented some of the first details about its upcoming 16nm finFET process. And at the same event, STMicroelectronics, CEA-Leti, Renesas, GlobalFoundries and Soitec presented a paper regarding an FDSOI technology, which features a 20nm gate length for the 14nm node and beyond.

For its part, TSMC described a 16nm finFET technology, which includes a 0.07um(square) SRAM, copper/low-k interconnects, high-k/metal-gate and other features for mobile system-on-a-chip (SoC) applications. The transistors achieved a short channel control with DIBL of <30 mV/V and a Idsat of 520/525 uA/um at 0.75V and Ioff of 30 pA/um for NMOS and PMOS, respectively, according to TSMC. Fin patterning and formation on bulk with 48nm fin pitch is realized using a pitch-splitting lithography technique. A metal pitch of 64nm is enabled using an advanced patterning scheme. On the FDSOI front, STMicroelectronics and others reported ultra-thin body and box (UTBB) devices with a gate length of 20nm and BOX thickness (TBOX) of 25nm. The technology featured dual-channel FETs, with a silicon channel for the NFET and a compressively strained SiGe channel for the PFET. Effective current (Ieff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.9V. “By incorporating strain into the channel and optimizing the RSD epitaxy and junction design, high-performing second-generation UTBB devices were developed, which enable continued scaling to 14nm and beyond,” said Qing Liu, senior staff engineer at STMicroelectronics.