Manufacturing Bits: June 25

Panel-level consortium
Fraunhofer is moving forward with the next phase of its consortium to develop technologies for panel-level packaging.

In 2016, Fraunhofer launched the original effort, dubbed the Panel Level Packaging Consortium. The consortium, which had 17 partners, developed various equipment and materials in the arena. Several test layouts were designed for process development on an 18- x 24-inch panel size. That phase of the consortium ended in 2019.

The new effort, called the Panel Level Packaging Consortium (PLC) 2.0, will continue to develop the technologies in the arena, including processes and materials. “Our plan is to start with the PLC 2.0 at the end of this year,” said Tanja Braun, deputy group manager at the Fraunhofer Institute for Reliability and Microintegration IZM.

After years of R&D, panel-level fan-out technology is finally beginning to ramp up in the market, at least in limited volumes for a few vendors.

In production for several years, today’s fan-out technologies involve packaging a die in a round wafer format in 200mm or 300mm wafer sizes. In panel-level fan-out, though, the package is processed on a large square panel. By increasing the number of die per substrate, a vendor could see huge productivity gains and lower costs over today’s fan-out processes.

There are various manufacturing challenges here. Plus, there is a lack of panel standards.

“The industry is making progress. There are a lot of new materials and equipment with a focus on panel-level packaging entering the market,” Braun said. “Companies are already in production or close to it, such as Samsung, PTI, Nepes and ASE/Deca.”

Photonic interposers
At the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas, ams, Fraunhofer, Imec and Vertilas presented a paper on a 3D silicon photonics interposer.

The technology, which enables Tb/s optical interconnects in data centers, involves double-sided assembled active components using through-silicon-vias (TSVs) on a silicon-on-insulator (SOI) technology.

“In this paper, we present the concept, fabrication, process and packaging of a 3D Si photonics interposer. This Si photonics interposer merges passive photonic and electronic functionalities within a single chip. The interposer is populated with active optical and electronic add-ons, which are flip-chip bonded to the interposer using thermo-compression bonding,” according to the companies in the paper.

“The interposer itself is then flip-chip bonded to a glass and Si carrier for further testing purposes. This integration concept enables a high connection density (Gb/s/mm²) by assembling 40Gb/s per channel opto-electrical components on both sides of the interposer,” according to the companies. “Communication between components on both sides of the interposer is enabled by optical and electrical TSVs with a 3dB bandwidth >28GHz. A single mode photonic layer, designed for 1.55μm wavelength is integrated within the interposer to be used for routing and switching of the optical signals.”

Active interposers
At ECTC, the Agency for Science, Technology and Research (A*STAR) presented a paper on a new active through-silicon interposer technology for advanced 2.5D/3D IC packaging. The technology paves the way towards new forms of packaging for advanced designs.

In the lab, A*STAR developed a 28nm FPGA (12.65mm x 12.34mm) and two 65nm I/O chips (4mm x 4mm).

The devices were placed on a 130nm active thin interposer using a flip-chip bonding process. The interposer incorporates an analog-to-digital converter (ADC), digital-to-analog converter (DAC) and an embedded power management unit.

The interposer has six metal redistribution layers (RDLs). “(The) TSV is arranged in a staggered array with a pitch of 140um,” said Jayasanker Jayabala from A*STAR. “(The interposer) noise suppression is done with grounded TSVs. Parallel with TSVs are the C4 bumps to increase current carrying capacity. Substrate C4 bumps are arranged in regular array with a 400um pitch. TSV is directly connected to the UBM of a C4 bump and there is no need for backside RDL for routing.

“This approach enables significant die-size reduction of the top die (usually in expensive 16nm CMOS or below technology node) to achieve system miniaturization and cost reduction,” Jayabala said.