Migrating 3D Into The Mainstream

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for ANSYS’ Semiconductor Business Unit; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Business; Kevin Yee, foundry director for Samsung Semiconductor; and Bapi Vinnakota, director for silicon architecture program management at Netronome, and Open Domain-Specific Architecture (ODSA) sub-project lead for Open Compute Project (OCP). What follows are excerpts of that conversation. (Part one of this discussion can be found here, and part two is here.)

SE: We have been talking about two approaches. One is chiplets, where each chiplet is designed in isolation, and the other is designing the whole stack as a single function. What implication does that have on tools that need to optimize in 3D? If you have a chiplet that goes on the stack, you still have some of the same issues, but you cannot cannot control everything.

Park: There are three things going on. First, we have the new paradigm for logical partitioning. This could be done with chiplets or multiple chips. Then we have the new packaging technologies coming on. That give us embedded bridges, thin-film fanout layers, silicon interposers, TSVs – so we have this new way of logically partitioning to get around Moore’s Law. We have new packaging technology that goes along with that. We have the ecosystem changing the OST/foundry relationship. If you add all of this up, you have a lot of moving parts, and this is part of the reason we spend a lot of time developing tools for early pathfinding. You can figure out a lot of things up front. It allows me to quickly make changes when I find out that something wont work. You need to have these tools, like a sandbox, that allow you to mock things up, do a quick thermal test, and optimize the connectivity paths between them to try and figure out what works way before you start the detailed design. We see a lot of customers now that used to spend 90% of their time implementing something, but now spend 20% of their time implementing and 80% figuring stuff out — pathfinding, exploring, looking for the right solution. That is because we now have so many technologies and they are being adopted because Moore’s Law is coming to an end. People are concerned, and they are looking at other alternatives.

Yee: I have a question for the tool guys. What are the biggest challenges right now? Is it the thermal stuff, is it the place-and-route, is it extraction and analysis, is the packaging portion of it?

Park: It is all of those.

Yee: But does one stand out more than another?

Park: I would say routing and resource sharing between chips in a stack. For the rest of it, I can meet with eight customers and they will all have different ideas about how they see the challenges.

Yee: That is the biggest challenge. Every customer is slightly different.

Chang: Since we do not have routing tools, I would say the toughest challenge is multi-physics analysis. Compared to 2.5D, the wafer-on-wafer, true 3D-IC design brings a lot of challenges. You may have wafer-on-wafer on the same node, say 7nm, and use a bump to connect them. You may have 7nm and 16nm, and you need to have an interlayer to do the routing redistribution and connect them together, so there could be different materials. In terms of multi-physics analysis, it’s about where are the thermal hotspots and the impact from different dies, the mechanical strength.

Yee: We have a problem with power delivery, too, when different technologies are involved.

Chang: Right, and power integrity, electromigration on the TSV layer, which is also important. These are all multi-physics issues. This is a lot more difficult than 2D and 2.5D.

Park: And you have to close timing across them.

Yee: There is a lot of black magic.

Ferguson: Ultimately, it all has to come together. When you place and route, you have to be aware of the multi-physics, all of the interactions, all of the possible failures so that you don’t route something that will not work.

Yee: It almost feels like exponential changes in the number of things that you have to consider now. Adding each new variable changes it exponentially.

Chang: For true 3D-IC design, the tools are falling behind the designs that people are doing.

SE: When you design a chiplet, you think it is bulletproof in every conceivable way. But then you put it next to another chip that starts bombarding it with noise that the original designers did not expect. System-level verification will need to bring in the models of everything at the right level of abstraction to do a different level of analysis.

Park: That is exactly right, and they have to work across different nodes and different technologies. With chiplets, one could be at 7nm, one at 20nm, one at 28nm, and one could be on CMOS and one on GaAs. The whole idea is packing and closing timing on the three chips on the package, and the package designer just has to connect those together, do a few connectivity checks, and they are good to go. You can’t do that anymore. You have to functionally validate everything, and for some you may need a full transistor layout while for others you have to use a high-level abstract model. And you have to be able to stitch all of those together. We have some technology that we offer in that space, but it is not perfect yet. What we are doing here touches everything in the flow. It is not like a new router or a new EM extraction tool. It is everything from early feasibility to tapeout. Every tool in the flow is impacted.

Vinnakota: An interesting idea is that when you sell a chiplet, you need an open way to physically describing the chiplet. Normally a chip is a 2D thing, but now when you are selling a chiplet and you have to describe it in three dimensions and start describing the surface, the height, a finite element map of its power profile, heat dissipation. Are companies that make chiplets willing to settle on a standard format to describe these things so that you can assemble chiplets from multiple companies into a tool flow? Do you exchange this information one-on-one with an NDA, or do you form an association where that kind of information goes into a database and you could build a chiplet design exchange? An interesting question is what can you be open about? If you can agree upon a format for the information, that is one step and is better than what we have today.

Yee: You talking about something like IP-XACT?

Vinnakota: Exactly.

Yee: Something that describes it enough so that you can interact and interoperability easier?

Vinnakota: Yes, you have things like bus I/O that describe the logical interactions. Now can I do something for the physical description and interaction?

Park: An important point to make is that we have mixed together chiplets and 3D, and they should not be mixed. If you do that you will confuse people. If they want to merge them together that is great, but in general if I were writing a paper or giving a talk, they are different technologies. Chiplet is a disaggregation of the SoC, and mostly today they are placed side by side. That is just a logical partitioning problem. 3D is a physical change. It used to be flat, but now I am stacking them on top of each other.

Chang: But a chiplet can go into a 3D-IC.

Yee: A chiplet could be in a 3D-IC, but 3D may not be used for chiplets.

Chang: For 3D IC design, when you do the routing, the multi-physics simulation – how did you verify? When we talk about a single SoC, you can do probing everywhere, but for a 3D IC stack, and you want to measure something in between – it is very difficult. So, this is another issue for metrology, and this is why people have to start doing in-chip monitoring. This has to be built into the design.

SE: We talked about some of the problems. How far away are we from it becoming a technology accessible to the general community?

Yee: It is accessible now. When will it become mainstream? That happens when we have sorted out the challenges that we have been talking about. Everyone thought that with the most advanced nodes, only the biggest guys would use it, but lots of people — big guys and small guys — are going there. The industry is driving them. I think the same will be true for 3D. It is accessible today and there are small companies doing it as well. How do we, as an industry, make it so that it is more mainstream and the merging of competitive tools working together in terms of standardization? All of that has to be worked out and that will make it easier for adoption.

Park: I agree. The flow is not perfect today, but you can tape out a 3D stacked design. There is a lot of work that will make it better.

Yee: Our job is to make it better and easier and cheaper. The semiconductor industry is based on cost, and it is up to us to make it cheaper so that everyone wants to use it.

Ferguson: What will happen is that we, as a collective ecosystem, will be creating more and newer approaches for connecting chiplets and chips together, and putting more and more of them together. So the flow will not be static. It will change. Moore’s Law is changing from more transistors on a chip to more chips into a package. How they get connected together will change. We have to learn and adapt as it goes. Our jobs will never be done. There will be some point where what we did two years ago is now mainstream.

Chang: Compared to a single IC, 3D configurations are plentiful. There are all kinds of 3D-IC design styles. That brings additional challenges. If we want to automate a 3D-IC design flow, it is not as easy as a single chip. CoWoS (TSMC’s Chip on Wafer on Substrate) is much easier than wafer-on-wafer and InFO (TSMC’s Integrated Fan-Out) and EMIB (Intel’s Embedded Bridge Multi-die Interconnect Bridge) design. All kinds of configurations make it very difficult.

Vinnakota: The hidden variable, which we haven’t talked about much, is software. All of these chips are likely to have software, and the programmer will perceive, or the developer will see, a performance difference between off-die transactions and on-die transactions. Either it is hidden from the developer — like it is with memory where you just see a memory transaction — or it has to be a standards-based interaction like some version of a protocol interface, where the developer knows exactly what to expect. Otherwise you will see a variation in performance from the programmer’s side.

Yee: As we go to 3D, it becomes a system approach. It is not a chip approach anymore. That means you have to look at all aspects of it. That is why companies are hiring board designers and as we go to 3D. It incorporates everything that you thought a system was before, with software, and now you have more.