NoC Your SoCs Off

By Ed Sperling

The network on a chip (NoC) approach is gaining ground as an essential part of a system on a chip (SoC), providing the same kind of time-to-market advantage that well-tested intellectual property blocks provide.

This follows almost eight years of hype about NoCs potential with little to show for it. Times have changed and there appear to be two main drivers, one technological and the other business-related. From a technology standpoint, the real key is that chip designs are becoming far too complex to create all the interconnects necessary to get an SoC out the door on time and on budget. From a business perspective, the downturn has cut into staffing of design teams so severely that most companies don’t have the manpower left to develop complex interconnects on a chip that also has multiple cores, multiple power islands, as well as shared busses and memory.

“The key trend that makes such technologies more important is simply the increasing levels of integration, which significantly increase the amount and complexity of the on-chip communication—particularly in the sharing of key resources such as external DRAM,” said Jim Hogan, a venture capitalist familiar with this market. “This complexity permeates every part of the SoC design, from the increasing fraction of circuit delay due to wiring at deeper process nodes up through the massively deeper pipelining required to keep modern DRAMs operating at high efficiency, to the QoS scheduling required to ensure that general purpose software on CPUs can co-exist with real-time communications and multimedia traffic. NoCs provide a structured framework for managing these growing complexities and will therefore become the dominant approach for complex SoCs.”

But structured does not mean standardized. Far from it, in fact. While NoCs fit into standardized EDA flows and work with standards, they are one of the key components that must radically change from design to design.

“At 45nm, and with some designs at 65nm, companies have started to see issues with interconnects” said Charlie Janac, CEO of Arteris. “Projects cost more, they last longer, or they’re being canceled. There’s more problem solving, and the interconnect is more important. When we had single-core chips, it was a choice between a mainframe versus distributed network computing. Now we’re dealing with four to six cores, algorithmic engines, graphics, peripherals and on-chip/off-chip memory. All of this requires more communication on a chip.”

Defining NoC

So what exactly is a NoC? Definitions vary, and likely will evolve as NoCs become both more necessary and more widely deployed. And some of the standard definitions are fuzzy at best. Wikipedia, for example, defines a NoC as “an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip.”

Most chip architects view NoCs as more of an evolutionary step than a radically new concept, though, with the difference being that a NoC is now a discrete part of the development process instead of including it as a piece of something else.

“I like to use the phrase ‘network on chip’ to describe what we do and have been doing for a few years,” said James Aldis, SoC architect at Texas Instruments. “My definition is based around the idea of the NoC being a separate component in the top-level assembly, with a point-to-point interface to each other top-level component. This is distinct from a traditional ‘bus’ where the bus is the top-level assembly. The alternative view is that a NoC is really something with a network-style architecture, where you send out bus requests and responses on the same wires. This alternative view means that the external interfaces of the NoC are not traditional ‘bus-style’ but rather ‘network-style.’ Transactions are captured in packets rather than being represented by separate address, data and command busses. This alternative view is not yet real in the IP industry. You can’t buy IP with this sort of interface on its boundary. It may be used internally in some companies.”

The NoC is particularly attractive at advanced process nodes because of the increasingly complexity and the ability to isolate some of that complexity in the network.

“With the advent of SOCs, a lot of complexity has moved into the interconnect. No one building such chips is really using the old “bus” paradigm anymore,” said Geert Rosseel, senior director at Pixelworks. “The interconnect now has to manage communication between IP blocks having very heterogeneous bandwidth and latency requirements and possibly living on different clock and power domains. The interconnect is now managing CPU-type requests with networking and real-time media (video and audio) traffic, usually all directed to shared resources such as memory. In my opinion, everyone building an SOC is already implementing some kind of complex on-chip communication system.”

But the NoC takes that one step further.

“What sets the concept of a NoC apart is the idea of developing an architecturally clean and unified approach to solving this problem,” Rosseel said. “You put all communication complexity in the network with the IP conforming to some simple interface standard. Once you have this ‘clean’ separation, you can develop an interconnect based on internal protocols that are optimized to meet the performance, area and power requirements.”

Looking forward and backward

The final caveat for most NoCs is that they have to embrace both new and existing technology. That includes a number of existing on-chip protocols, the Open Core Protocol (OCP), ARM’s Advanced extensible Interface (AXI) and AMBA High-Performance Bus (AHB), as well as an alphabet soup of proprietary and lesser-known acronyms.

Ian Mackintosh, chairman of OCP-IP, said the real key is to maintain openness, while embracing existing standards. “The world is heterogeneous,” Mackintosh said. “People have worked up from single bus generators to intelligent networks on chips where you need predictive performance of the NoC.”

OCP-IP has been working on a way to standardize NoC benchmarking to help sort through years of attempts to get this right. For further reading on this subject, check out the white paper entitled: “An Iniative Towards Open Network-on-Chip Benchmarks.”