Power/Performance Bits: Oct. 11

Getting to 1nm

Researchers at the Lawrence Berkeley National Laboratory, UC Berkeley, University of Texas at Dallas, and Stanford University created a transistor with a working 1nm gate from carbon nanotubes and molybdenum disulfide (MoS2).

“The semiconductor industry has long assumed that any gate below 5 nanometers wouldn’t work, so anything below that was not even considered,” said first author Sujay Desai, a graduate student at Berkeley Labs. “This research shows that sub-5-nanometer gates should not be discounted. Industry has been squeezing every last bit of capability out of silicon. By changing the material from silicon to MoS2, we can make a transistor with a gate that is just 1nm in length, and operate it like a switch.”

The device used MoS2 for the channel material, a single-walled carbon nanotube for the gate, and a zirconium dioxide (ZrO2) gate dielectric on a 50nm SiO2/Si substrate. It exhibited excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~10⁶. Simulations showed an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

Schematic of a transistor with a molybdenum disulfide channel and 1nm carbon nanotube gate. (Source: Sujay Desai/Berkeley Lab)

Both silicon and MoS2 have a crystalline lattice structure, but electrons flowing through silicon are lighter and encounter less resistance compared with MoS2. That is a boon when the gate is 5nm or longer. But below that length, a quantum mechanical phenomenon called tunneling kicks in, and the gate barrier is no longer able to keep the electrons from barging through from the source to the drain terminals.

Because electrons flowing through MoS2 are heavier, their flow can be controlled with smaller gate lengths. MoS2 can also be scaled down to atomically thin sheets, about 0.65nm thick, with a lower dielectric constant.

The work is still a proof of concept, said Berkeley Lab faculty scientist Ali Javey. “We have not yet packed these transistors onto a chip, and we haven’t done this billions of times over. We also have not developed self-aligned fabrication schemes for reducing parasitic resistances in the device. But this work is important to show that we are no longer limited to a 5nm gate for our transistors. Moore’s Law can continue a while longer by proper engineering of the semiconductor material and device architecture.”

Quantum photonic circuits

Scientists at the Westphalian Wilhelm University of Münster (WWU) and the Karlsruhe Institute of Technology (KIT) succeeded in placing a complete quantum optical structure on a chip.

“Experiments investigating the applicability of optical quantum technology so far have often claimed whole laboratory spaces,” said Professor Ralph Krupke of KIT. “However, if this technology is to be employed meaningfully, it must be accommodated on a minimum of space.”

The light source for the quantum photonic circuit was carbon nanotubes, which emit single light particles when excited by laser light. That carbon tubes emit single photons makes them attractive as ultracompact light sources for optical quantum computers. “However, it is not easily possible to accommodate the laser technology on a scalable chip,” said physicist Wolfram Pernice of WWU.

Carbon tube (center) as a photon source and superconducting nanowires as receivers constitute part of the optical chip (Photo: W.Pernice/WWU)

On this chip, all elements are triggered electrically, requiring no additional laser systems, a marked simplification over the optical excitation normally used.

“The development of a scalable chip on which a single-photon source, detector, and waveguide are combined, is an important step for research,” said Krupke. “As we were able to show that single photons can be emitted also by electric excitation of the carbon nanotubes, we have overcome a limiting factor so far preventing potential applicability.”

The researchers note, however, that the work is fundamental research and it is not yet clear whether and when it will lead to practical applications.

Data center on chip

Researchers from Washington State University and Carnegie Mellon University presented a preliminary design for a wireless data-center-on-a-chip at the Embedded Systems Week conference in Pittsburgh.

Data centers are well known as energy hogs, and they consumed about 91 billion kilowatt-hours of electricity in the U.S. in 2013, which is equivalent to the output of 34 large, coal-fired power plants, according to the National Resources Defense Council. One of their major performance limitations stems from the multi-hop nature of data exchange.

In recent years, the group designed a wireless network on a computer chip. The system includes a tiny, low-power transceiver, on-chip antennas and communication protocols that enable wireless shortcuts.

The new work expands these capabilities for a wireless data-center-on-a-chip. In particular, the researchers are moving from two-dimensional chips to a highly integrated, three-dimensional, wireless chip at the nano- and microscales that can move data more quickly and efficiently.

The team believes they will be able to run big data applications on their wireless system three times more efficiently than the best data center servers.

In the future, the researchers will evaluate the wireless data center to increase energy efficiency while also maintaining fast, on-chip communications, and hope it could someday enable personal cloud computing possibilities.

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