Get Ready For Integrated Silicon Photonics

Long-haul communications and data centers are huge buyers of photonics components, and that is leading to rapid advances in the technology and opening new markets and opportunities. The industry has to adapt to meet the demands being placed on it and solve the bottlenecks in the design, development and fabrication of integrated silicon photonics.

“Look at the networking bandwidth used across cloud computing, search and social networks,” says Brian Welch, director of product marketing for Luxtera. “These guys run mega data centers and they just consume outrageous amounts of bandwidth — far in excess of all of the other markets put together. The next place that could rival that scale is the 5G rollout for radio.”

But it is not just about bandwidth anymore. Integrated silicon photonics has the ability to fundamentally change some notions of computing. The industry is just beginning to see what may be possible.

The importance of silicon
In the past, photonics was fabricated using specialty fabs, often based on Indium Phosphide (InP). “Silicon has allowed companies to access the larger scale of manufacturing,” asserts Radha Nagarajan, CTO for Inphi. “Silicon uses 8-inch or 12-inch wafers (200mm or 300mm), versus a 3-inch or at most 4-inch wafer (100mm) for InP. The scale of manufacturing is different. Silicon also draws upon manufacturing processes, such as implants. These are very commonly used in silicon photonics, but not as common in InP, where etch is used to form certain structures and then you passivate them.”

Luxtera’s Welch notes that in addition to being low cost, silicon photonics is incredibly high volume. “If you are using a CMOS foundry, their capacity is unparalleled,” he says. “In the past, slow production has delayed adoption of optical solutions

Another advantage of going to 300mm is that foundries are more likely to be using advanced fabrication technologies. “While you don’t need great lithography for optics, it doesn’t hurt,” says Welch. “The structures are huge compared to transistors, and most optical structures have infinite bandwidth, so they don’t need to scale like you need to scale CMOS to make it faster.”

Fig. 1: Integrated photonics. Source: Luxtera

In fact, talking about node sizes doesn’t really make sense for optics. “The wavelength of a photon is quite a bit larger than the wavelength of an electron,” points out Nagarajan. “This is why electronics can go to a 7nm node. However, standard silicon photonic devices are at 130nm or 180nm node, and that is usually using a 245nm lithography line. Optical devices are different from electrical in that they are phase-sensitive. Sidewall roughness and losses matter. When these things are important it is not the node that is important. It is the quality of the lithography and etch that goes with the finer node, but at a larger scale.”

While you may not want to use a 7nm node, the development for that may indirectly help. “All of the progress we have made towards having reduced line roughness on small gates are applicable,” points out Gilles Lamant, distinguished engineer at Cadence. “The foundries are investing in making the yield and the control of photonics processes better. You see that when you hear GlobalFoundries say that they are moving their platform to the larger wafer fabs or the more modern wafer fabs. This not only means more die per wafer, but also means they are targeting equipment that is more advanced and to have better control.”

The problem now is that photonics does not use a traditional CMOS process, and that has limited the number of foundries willing to manufacture the devices. “You want to use all of the tools that exist in the foundry and we want as few deviations as possible,” says Welch. “We do not want a special line or special tools. We want our wafers to run in the same processes as advanced CMOS. That is how we get the cost and the scale. A lot of work went into the technology, and it seems quite simple in that regard, but it is challenging.”

And certain challenges remain. Nagarajan points to a big one. “You need Germanium as a detector, and pure Germanium growth remains a challenge.”

Integration
Integration is the driver for data centers. “Integration really matters because it drives down costs,” says Welch. “As you optimize for cost or power, you will evolve towards more integration. So you can get closer to the switch, until eventually you are in the switch and achieve maximum density. This was the same for copper. It used to have discrete PHYs, but over time they got integrated at higher densities in the back of the switch itself. The same will play out in optics.”

In photonics there are two typical approaches to integration. The first uses hybrid dies, which have photonics elements directly on the CMOS die so CMOS transistors are on the same substrate as the photonic elements. This is the approach taken by Luxtera. However, most people still do a multi-chip design, which has a photonics die and an electrical CMOS die.

“The photonics die is generally lower cost to manufacture,” says Chris Cone, product marketing manager in the Custom IC design group of Mentor, a Siemens Business. “They are generated at a lower technology node such as 130 or 65nm, and the photonics dies tend to be larger. This means they can be flip-bonded, with a CMOS die bonded on top of it. We are seeing large strides in this area. Imagine a CMOS die flip bonded on top of a photonics die, and this die is somewhat larger so you can use it as an interposer. Then you need access to the CMOS die and that would require some form of through-silicon vias (TSV) approach to gain access to the electrical signals.”

One significant problem remains. The laser itself. “A major issue is the integration of the active optical elements, which are typically compound semiconductor-based lasers,” says Martin Eibelhuber, deputy head of business development for the EV Group. “The performance of these lasers cannot be met by silicon-based devices and thus heterogeneous material integration is required, which is not common to a standard CMOS infrastructure. Direct wafer bonding has proven to be an excellent method of combining different materials — allowing high-quality integration at low costs. Due to geometrical constraints, a full wafer-to-wafer bonding approach is not preferred for silicon photonics and thus collective die transfer processes utilizing plasma activated direct bonding have been developed.”

Design flows
To make a technology more accessible requires tools, processes and flows. “We are at the beginning of our efforts to raise photonic design to higher levels of abstraction while adding more automation,” said Tom Walker, group director of R&D for Synopsys’ Optical Solutions Group. “Both of these factors are important for enabling a wider range of designers to create custom photonic integrated circuit designs.”

It all starts with the PDK. “Both Synopsys and Cadence are increasing their offerings in this area,” says Nagarajan. “Synopsys just acquired a company in this area (PhoeniX Software). There is a need for the PDK to be automated, to be incorporated with Mentor tools that does design rule checking (DRC) and the Cadence tools that do analog/digital simulation and the equivalent for Synopsys. There is a whole suite of optical tools that need to get ported into these flows. This is slowly happening.”

Several foundries have announced PDKs this year. Then you can go one stage up in abstraction.

“The design process is divided into different levels,” explains Walker. “Each level exposes functionalities of increasing abstraction to designers, while hiding the inner workings of the level underneath. The first level corresponds to the physical layout. Here, the geometry and the material properties are controlled in order to create structures that define components and connections. The level above is the circuit level, where the signal behavior is defined by connecting individual components into circuits.”

In the analog world, the next level of abstraction is often called parameterized cells or PCells. “If your design is primarily PCell-based from standard foundries, the design environment lends itself to some automation,” continues Nagarajan. “You can buy an IP core and drop that in. If you are at the high-end, you are designing on the bleeding edge it tends to be an expert driven process. The tools are getting there although they are nowhere near the sophistication of electronics or the IP cores that are commonly available, but some of the foundries are starting to offer PCells.”

The flip side of design is verification. “When you are talking about the top to bottom of a rack or the left to right of a card, being able to have a full-system simulation starts to become very interesting,” says Cadence’s Lamant. “You need to have AMS coupled with an optical simulator. Without simulation you just plan to be robust and put in enough repeaters, but for shorter distance you want to try and optimize it and minimize the energy consumption.”

The integration of optical components also creates some interesting new challenges. “Light has a tendency to bounce back,” adds Lamant. “So you have forward propagation of the light, but there is a certain amount of light that will bounce back and you do need to model that. This is where having an optical simulator in the mix really helps. If you have a methodology where you use a mathematical model for propagating signals, such as Verilog-A, propagating backwards requires a lot of extra equations.”

Another set of problems arise at the point where electrical and photonics come together. “When you drive a photonic interface, you run into the problem of a lot of noise and a lot of heat, and that has to be accounted for,” says Mentor’s Cone. “Nobody has been providing that kind of capability. It all comes down to the interface, which is very high-speed, running at tens of Gigabits per second, a switch driving a junction or phase shifter on a modulator, and that generates an EMI signature that you would have to account for. Similarly, going from a photodetector, you would have a very sensitive input coming into a transimpedance amplifier. You have to shield this from noise coming from other parts of the circuitry.”

This electrical activity, and the heat that it generates, can create difficulties for the optics. “You can see tremendous variation of the phase of the light just by changing temperature by 1°C,” points out Lamant. “There are some nice ways to tune the optical circuits, and while this may be an advantage, all of the electronics around me are very quickly making more than 1°C variation. So it is a very sensitive tuning mechanism and also a big problem. This is an area of investment and research. We need to have a better understanding of the thermal effects in a dynamic way. For electronics, it is normally looked at as a second-order effect. But for optical, thermal is a first-order effect. If you look at a component from a PDK from a foundry, you will see a lot of thermally adjusted components. So it is not something that can be left until the verification stage. It is a first-order effect.”

Lamant explains that a photonics circuit needs to find a thermal equilibrium. “When you want to create zeros and ones in photonics, you are either trying to align the phase or misalign them to have either constructive or destructive interference. You are moving things forward or backward by heating things up a bit to readjust the phase shift that is influenced.”

EDA is responding to the challenges. However, Cone has a warning: “Photonics is quite different from electronics and we need to provide solutions to the community to meet their needs rather trying to force the photonics community to adhere to the strict rules of EDA design, which I don’t believe is the right approach.”

A bright future
While photonics will never follow a path like electronics and Moore’s Law, the industry is just beginning to ramp up to the possibilities of photonic circuits. Lamant points to one interesting development from MIT. “Light Matter has a photonics multiplier that is used in machine learning to apply matrix coefficients. The photonics circuit itself is remarkably simple but the function that is being performed is very complex.”

Matrix multiply is the performance limiter in machine learning and consumes a large amount of power. With an optical equivalent it can be performed much faster and with a tiny amount of power.

Other applications are likely to be found. Lamant warns, though, that “one important consideration is that the data has to be converted into a form suitable for the optics, and that takes energy. So one of the tradeoffs is whether it is worth converting the electronic information into light so that it can be consumed and processed within an optical accelerator. Or is it better to use it as electronics and to pay the higher costs? This is a system-level tradeoff.”

Cone points to another interesting line of research. “Look at HPE Labs and the Machine, which is a form of memory-driven computing. They provide a vision for the future of computing, which is photonics-based.”

This development assumes that with silicon photonics you have large sets of nodes connected through a single fiber and they are all talking to each other almost instantaneously. “This has the effect of transforming our knowledge of system-on-chip architectures, where everything is based on electrical connections,” says Cone. “We are seeing companies realize that they do not need to use traditional architectures, where everything is modular and talks through some interface. Now everything can talk to each other at the same time. We are barely scratching the surface of seeing this kind of transformation and have that push into the electrical aspects of the products.”

The world of integrated silicon photonics is getting a lot closer and the necessary tools and flows are coming into place. Soon it will be up to the industry to come up with the most innovative ways to utilize it.

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