Silicon-based Power Semis Face Challenges

Suppliers of power semiconductors continue to develop and ship devices based on traditional silicon technology, but silicon is nearing its limits and faces increased competition from technologies like GaN and SiC.

In response, the industry is finding ways to extend traditional silicon-based power devices. Chipmakers are eking out more performance and prolonging the technology, at least in the near term.

Power semiconductors are specialized transistors used in a multitude of low- to high-voltage applications, such as automotive, industrial, power supplies, solar, and trains. These transistors operate like switches in devices, allowing the electricity to flow in the “on” state and stop it in the “off” state. They boost the efficiencies and minimize the energy losses in systems.

For years, the power semiconductor market has been dominated by silicon-based devices, namely power MOSFETs, super-junction power MOSFETs, and insulated-gate bipolar transistors (IGBTs). First commercialized in the 1970s, these devices are found in nearly every system today. These products are mature and inexpensive, but they also have some drawbacks and are reaching theoretical performance limits in some cases.

That’s why many suppliers are also developing and shipping a newer class of power devices based on two wide-bandgap semiconductors — gallium-nitride (GaN) and silicon carbide (SiC). In the market for some time, GaN- and SiC-based power devices compete against silicon IGBTs and MOSFETs in various segments. GaN and SiC devices are more efficient, but they also are more expensive.

Taken as a whole, these various types of power semiconductors offer options to customers, but they also add a level of confusion. As it turns out, no one power device can meet all requirements in systems. That’s why customers need a range of options with different voltage ratings and price points.

GaN and SiC devices have grabbed the spotlight these days. They are newer, and provide an assortment of impressive properties. But the well-established silicon-based devices are also important, and they aren’t going away anytime soon. Silicon-based devices continue to advance, albeit more slowly than in previous years.

“Today, we see that silicon will still be the dominant form of the power MOSFET to the tune of about 60% of the market, even with the advent of wide-bandgap technology,” said Bob Yee, director of applications management at Infineon, the world’s largest supplier of power semiconductors. “Wide-bandgap will fill and take the space of silicon where it adds more value, and will enable new applications where silicon cannot. That is to say, wide-bandgap is complementary to silicon. But silicon will still be the workhorse for the foreseeable future.”

In other words, there is a place for all technologies. All told, silicon-based power semis, including IGBTs and MOSFETs, still make up about 80% of the overall market. There are several events taking place in the silicon arena, including:

• Vendors are shipping new families of silicon-based power MOSFETs, super-junction devices and IGBTs.
• In R&D, the industry is advancing silicon-based MOSFETs and IGBTs.
• Lam Research and others have developed new equipment for power semis.

Fig. 1: How today’s power switches are categorized. Source: Infineon

What are power semis?
Power semis are used in the field of power electronics. Using solid-state devices, power electronics control and convert electric power in various systems, such as cars, motor drives, power supplies, solar and wind turbines.

These devices are different than conventional metal–oxide–semiconductor field-effect transistors (MOSFETs). Today’s digital CMOS FETs consist of a source, gate, and drain built across the top of the silicon. In operation, a voltage is applied to the gate, causing current to flow from the source to the drain.

In contrast, IGBTs and most power MOSFETs are vertical devices, where the source and gate are on top of the device and the drain is on the bottom. In operation, a voltage is applied to the gate and electrons move in a vertical direction. Vertical orientation supports higher currents and voltages.

There are other differences, as well. In conventional MOSFETs, chipmakers shrink feature sizes of transistors at each generation, enabling chips with higher transistor density. In power devices, vendors are also shrinking transistors, but not to the extent of digital CMOS.

“If you think about MOSFETs and IGBTs, they are going through their own trajectory in terms of scaling and efficiencies,” said Michelle Bourke, senior director of strategic marketing at Lam Research. “Some may say the features are big compared to CMOS. But the verticality and the profile control that’s needed in order to reach that device performance is as challenging as some of the CMOS issues that we run into within Lam. So while the features are still large from a device perspective, from a development perspective it’s one of the most challenging processes that we’ve done. We are enabling that to happen.”

Generally, for power semis, the most important considerations are other parameters, such as voltage (V), Rds(on), and gate charge. Each power semi device has a voltage rating (V). “The ‘V’, as in VDSS, is the maximum allowed operating voltage, or drain-source voltage specification,” explained Alex Lidow, chief executive of EPC.

On-resistance, or Rds(on), is the resistance value between the source and drain. The gate charge is the amount of charge that turns on the device. Ron x A is important. “Cost optimization in the semiconductor business has always been linked to die shrink. This rule also holds true for power devices. Ron x A is a key figure of merit that describes the silicon area needed to deliver a certain device performance of a power device. Typically when we develop new power technologies the cost advantage we get from the area gain by lowering the Ron X A for a new technology outweighs the additional cost of a typically more complex production process. These cost benefit can be handed over to customers and are the core of cost down roadmaps,” Infineon’s Yee said.

Several power semi options are available to suit different applications. On the silicon front, the choices include power MOSFETs, super-junction power MOSFETs and IGBTs. Considered the least expensive and most popular devices, power MOSFETs are used in adapters, power supplies and other products. They are used in 25- to 500-volt applications.

Super-junction power MOSFETs, which are souped-up MOSFETs, are used in 500- to 900-volt systems. Meanwhile, the leading midrange power semiconductor device is the IGBT, which is used for 1,200-volt to 6.6-kilovolt applications.

Silicon-based power devices compete against GaN and SiC in various segments. Both GaN and SiC have some impressive properties. SiC offers 10X the breakdown electric field strength and 3X the band gap of silicon. GaN surpasses those figures.

“Wide-bandgap semiconductors have key advantages, but they are going to live in parallel with silicon-based technologies,” said David Haynes, managing director of strategic marketing at Lam Research. “Silicon-based technologies are going to be around a long time. They are very well established. And there’s a lot of research and technology development going on in silicon-based power devices.”

Fig. 2: Planar vs. trench MOSFET die layers. Source: Infineon

In 1969, Hitachi described the world’s first power MOSFET. Over time, a growing number of companies entered the power MOSFET market and it grew into a big business.

In 2020, the overall power MOSFET market was a $7.5 billion business, according to Yole Développement. The market is growing at a modest 3.8% pace per year, according to Yole. Infineon is the largest power MOSFET supplier, followed by a host of others, according to Yole.

Used in 25- to 500-volt applications, power MOSFETs are found in nearly every system. Typically, these devices are manufactured in 200mm and 300mm fabs.

Over the years, power MOSFETs have improved. In the 1970s, the first devices were based on planar gate structures, according to B. Jayant Baliga in his book entitled “Fundamentals of Power Semiconductor Devices.” Baliga, the inventor of the IGBT, is a professor at North Carolina State University.

This power MOSFET had a source and gate on the top, and a drain on the bottom. It is sometimes called a planar power MOSFET.

Then, in the 1990s, vendors moved to a trench-based gate structure, according to Baliga. It’s still a vertical device. But instead of having a horizontal gate structure, a trench-based power MOSFET has a vertical gate in the structure. Trench-based power MOSFETs enable higher densities with smaller die sizes.

Over time, suppliers used both planar and vertical gates, depending on the application. They also used various innovations from the design and manufacturing fronts, which enabled them to continue improving their devices.

Recently, for example, Infineon introduced its latest power MOSFET family—the OptiMOS 6. The devices have an 18% lower Rds(on) than the previous generation.

Other suppliers are shipping new power MOSFETs. Plus, vendors are working on newer technologies. For example, Applied Novel Devices (AND) is developing power MOSFET with GaN-like performance. SkyWater is AND’s foundry partner.

“With each iterative generation of silicon, we’ve reduced the cell pitch of the trench,” Infineon’s Yee said. “This is to say we are lowering the Rds(on) x A (area). This results in a lower figure of merit, which allows the application to switch faster. This reduction in Rds(on) x A allows suppliers to lower the overall cost of the MOSFET, while at the same time increasing the performance.”

Still, there are challenges with advancing power MOSFETs. “To further reduce the figure of merit [Rds(on) x gate charge], while maintaining the device thermal characteristics is always a challenge,” Yee said.

While vendors are finding ways to eke out more performance with new devices, they also are tweaking their manufacturing processes in the fab. Generally, the power MOSFET process is mature, but there are some issues.

In the fab, vendors use many of the same process steps for both planar- and trench-gate power MOSFETs, but there are key differences. For both technologies, the first step is to deposit a thin N+ epitaxial layer on a substrate. This layer is called a drift region.

A mask layer is deposited on the device. The mask layer covers the top of the device, except for the edges on each side of the device. The edges are implanted with a P-type dopant, according to NC State’s Baliga.

The thickness of the epi stack is key. Epi layer thickness is directly linked to the blocking voltage of the eventual device. “(For example), a thicker and more lightly doped epi (stack) supports higher breakdown voltages, but with increased on-resistance,” according to Alpha and Omega Semiconductor.

Then, a trench is formed on the device. The dimensions of the trench are defined by the original design. In some cases, a trench size could measure 1.5μm and smaller.

To form a trench, another mask layer is deposited on the device. This time, the middle portions are exposed, which are implanted with N-type dopants.

To form a trench, an oxide is deposited on the surface. The trench is patterned and then etched. The trench is filled with gate material. Finally, a source and drain are formed.

All of these steps are important, particularly the etch process. Using an etch tool, the trenches in power MOSFETs are generally etched using an SF₆/O₂ plasma process.

“That’s the approach that most people use. Sidewall smoothness and bottom rounding is key. The SF₆/O₂ approach gives you a reasonable selectivity to the hard mask and allows you to have relatively high depths and aspect ratios,” said Dave Thomas, vice president of product management at SPTS, a KLA company. “One of the limitations with the SF₆/O₂ continuous approach is the absolute depth that you are going to achieve. You can only reach a certain point where you can no longer maintain sidewall quality. This is due to the delicate balance between keeping the silicon etch from moving and protecting the etch sidewall through oxidation (i.e. balancing the ratio of SF6 and O2). Therefore for deeper structure the Bosch process is more appropriate. Then, however, the key point switches back to sidewall smoothness through minimizing the Bosch etch scallops.”

Advancing super-junction MOSFETs
Power MOSFETs, meanwhile, have some limitations. So years ago, the industry developed super-junction power MOSFETs. Still based on silicon, super-junction devices are used in 500- to 900-volt applications.

These devices resemble power MOSFETs. The big difference is that super-junction MOSFETs consist of vertical high-aspect ratio P/N columns within the structure, which has some advantages.

“Super-junction power MOSFETs enable more power in a smaller amount of space. Secondly, it offers reliability for mission-critical applications,” Infineon’s Yee said. “Successively with every generation, we are improving the device parametrics, such as 1) Rds(on); 2) lower gate charge; and, 3) Eoss (energy stored in output capacitance).”

Fig. 3: Cross section of standard MOSFET (L) and super-junction MOSFET (R). Source: Infineon

Indeed, these devices continue to evolve. For example, Infineon’s super-junction power MOSFET family, called CoolMOS, is currently in its seventh generation. A new generation is in the works. In addition, Alpha and Omega, Magnachip, Rohm, Toshiba and others are shipping new super-junction power MOSFETs.

However, super-junction technology, in general, is reaching its limits. “There is a physical limit with super-junction power MOSFETs in terms of Rds(on) x A improvement after 20 years of evolution,” Yee said. “But there will still be a few generations of super-junction improvements. The advent of wide-bandgap will undoubtedly take over this quest for performance gains in the coming years. To reiterate, super-junction MOSFETs will co-exist with wide-bandgap technologies for the foreseeable future.”

Vendors still are finding ways to extend super-junction devices, but there are some challenges. Traditionally, to make super-junction MOSFETs in the fab, vendors stack multiple epitaxial layers on top of each other on a substrate. At each layer, there is a masking and implant step. This in turn forms P-type pillars in the device. Then, the source, drain and gate are formed.

This approach works, but the resulting N- and P-type structures are larger. That, in turn, impacts die size.

So in 2008, Denso developed a different approach, which has gained steam in the market. In this flow, an N-type epitaxial layer is deposited on the substrate. Next, using an etch tool, vertical trenches are formed in the epitaxial layer at high aspect ratios.

Then, P-type materials are deposited in the trenches, creating P-type pillars, according to Denso. This results in a device with alternating P/N columns. A gate, source, and drain are formed.

“(This approach) improves the tradeoff relationship between breakdown voltage and specific on-resistance,” said Denso’s Jun Sakakibara in the original 2008 paper.

There are some manufacturing challenges here, namely making high-aspect ratio (HAR) trenches within the structure.

“There are different mechanisms of making super-junction MOSFETs,” Lam’s Haynes said. “Many of them involve high-aspect ratio trench etch. And those aspect ratios can be 40:1 to 50:1. And increasingly, the aspect ratios can be as high as 80:1 or 100:1. It’s a new set of challenges for silicon etch. Unlike IGBT or conventional MOSFET trenches, these extremely deep, HAR super-junction MOSFET trenches cannot be etched using the type of steady state etching process used in CMOS manufacturing.”

In other words, it requires a different solution, namely a reactive ion etch (RIE) tool. “They need to be etched using a deep reactive ion etch process, where the process is switched between etching and deposition of sidewall passivation to enable deep etch capability,” Haynes said.

In RIE, the first step is to etch out a part of the structure and then passivate it. Then, you repeat the process until the etch is completed. This is called the Bosch process.

Over the years, several vendors have developed RIE tools for these applications. Lam, for one, recently introduced a new RIE tool design to meet the HAR challenges here. Lam’s new tool, called the Syndion GP, provides deep silicon etch capabilities for all power devices and other products. It supports 200mm and 300mm wafers.

“Our customers making power devices may be making IGBTs, MOSFETs and SJ-MOSFETs in the same production line,” Haynes said. “So when developing the Syndion GP tool, we wanted to deliver capability for both steady state and deep RIE processes in the same tool.”

What’s next for IGBTs?
IGBTs, meanwhile, remain the leading mid-range power device. IGBTs are vertical devices that combine the switching speeds of MOSFETs with the conductivity of bipolar devices.

IGBTs were a $5.4 billion business in 2020, and are expected to grow by 7.5% per year, according to Yole. Fuji, Infineon, Littlefuse, Mitsubishi, On Semiconductor, Toshiba and others compete here.

These devices are used in automotive, consumer and industrial applications. In some battery-electric vehicles (BEVs), IGBTs are used for the traction inverter, which provides traction to the motor to propel a vehicle.

Fig. 4: IGBT cross-section showing internal connection of MOSFET and bipolar device. Source: Wefoij/Wikipedia

Tesla is using competitive SiC power devices for the traction inverter in its Model 3 BEV. Going forward, BEV makers will likely use both IGBTs and SiC devices for the power inverters.

Over the years, IGBTs have improved. Last year, Infineon introduced new modules based on its seventh-generation IGBT family. Using a micro-pattern trench technology, the devices have a 24% lower switching loss than the previous products.

Like power MOSFETs, IGBTs consist of either planar or trench gate structures. In the more advanced trench-based IGBTs, the process starts by depositing four alternating epitaxial layers (P-N-P-N) on a substrate.

The surface undergoes a P-type implantation step. Then, to form a trench, the structure is patterned and etched. The trench structure is then filled with a gate material. Finally, using a deposition technology, an emitter is formed on the top, while a collector is developed on the bottom.

IGBTs have been around for decades, but the latest devices have several manufacturing challenges. “If you take IGBTs, there’s been a shift in reducing the on-resistance by making thinner and thinner wafers, while also increasing the power density,” Lam’s Haynes said. “And as you increase the power density, you increase the density of the trenches. You go from cell arrays that used to be square or maybe hexagonal kind of arrays to very densely packed trenches.”

The aspect ratios of the trenches also have increased. “Now, you’re using feature sizes that are maybe 7 to 10 microns deep. Aspect ratios are increasing as the pattern density comes closer,” Haynes said. “But in the RIE etch process, you need good profile control. These operate at very high voltages. Any misshape of the trench, or any non-uniformity of the trench profile, can lead to breakdowns.”

There are other challenges. “On the front side of the wafers, you are making contact metalization to the gate and source (MOSFET)/emitter (IGBT) connections. Because of the high currents involved with power devices, the metal has to be thicker than regular semiconductor devices,” said Chris Jones, senior director of PVD product management at SPTS, a KLA company. “The metal, usually an Al alloy deposited by PVD (typically AlSi or AlSiCu), and can be anything in the region of 3μm or up to 10μm thick. Contacts tend to be long trench-based structures, but round or slotted contact can also exist. Dimensions are typically from 1-2μm wide with a low aspect ratio. But as people go to more advanced devices, they might shrink the contact dimensions to 0.5μm width, with 2:1 aspect ratios. It’s relatively easy to put aluminum into a low aspect ratio contact. But to squeeze it into narrow gaps, you must use more advanced processes.”

Fig. 5: Power device IGBT process flow. Source: ULVAC

Nonetheless, suppliers continue to develop silicon-based IGBTs. Then, in R&D, suppliers and universities are working on newfangled devices.

At the 2020 IEDM conference, for example, several entities presented a paper on a 3.3kV back-gate IGBT (BC-IGBT). The University of Tokyo, Mitsubishi, Toshiba and others contributed to the work.

The BC-IGBT consists of gates on the top and bottom of the structure. “A major drawback of an IGBT is its relatively low switching frequency due to the accumulation of charge carriers in its base region,” said Takuya Saraya, a researcher from the University of Tokyo, in the paper. “By using the back side MOS gate for accelerating the electron drain and blocking of the hole injection, more than 60% reduction of turn-off loss was achieved.”

One way to develop a back-gate IGBT is to fabricate two separate devices and then bond them together. But that adds cost to the equation.

In the BC-IGBT technology, researchers developed a conventional IGBT. Then they implemented a conventional trench process on the bottom of the device. Both gates were aligned.

Conclusion
Silicon-based power semis will be around for a long time, and there is no indication they will ever go away. But GaN and SiC devices are making inroads in a big way. As a result, system manufacturers have several options to meet power semiconductor needs.

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