Technical issues increase, costs go up, and not all markets will benefit.

There are multiple layers in which machine learning can help with the creation of semiconductors, but getting there is not as simple as for other application areas.

Machine learning needs techniques to prevent adversarial use, along with better data protection and management.

Funding is free-flowing for the field, but hurdles persist.

New lithography, equipment required as packaging continues to scale.

Design challenges and tool flow gaps emerge, but so do real-world PPA metrics.

As cloud services adoption soars, datacenter chip requirements are evolving.

Device degradation becomes limiting factor in IC scaling, and a significant challenge in advanced SoCs.

How cost-sensitive are IoT edge devices, what are the real drivers for this industry, and what is the impact on EDA and IP?

Clocks are power- and area- hungry, and difficult to distribute in a controlled manner. What is being done to reign in these unwieldy beasts?

Dynamic power density and rising leakage power becoming more problematic at each new node.

Building a power delivery network with the low implementation overhead becomes more problematic at advanced nodes.

The physical layer interface is necessary for a chip to access the outside world, but it threatens to consume increasing portions of the power budget. What can be done to prevent a PHY limit?