Mark Bohr opens up on the company’s push into multi-chip solutions, and upcoming issues at 7nm and 5nm.

Foundry unit rolls out ambitious plan down to 4nm, along with 18nm FD-SOI and advanced packaging developments.

Demand is up, capacity is flat. A look at what’s behind this imbalance.

Technology begins to twist in different directions and for different markets.

Part 2: Heterogeneity and architectures become focus as scaling benefits shrink; IP availability may be problematic.

So far there is not widespread adoption, but many see change as inevitable.

Design challenges and tool flow gaps emerge, but so do real-world PPA metrics.

As cloud services adoption soars, datacenter chip requirements are evolving.

With few measurable methods to assess analog quality, it’s not clear how that can impact safety-critical applications.

Clocks are power- and area- hungry, and difficult to distribute in a controlled manner. What is being done to reign in these unwieldy beasts?

Modern electronics relies heavily on antennas, but companies still make mistakes. That’s about to change.

At 10nm and 7nm, overdesign can affect power, performance and time to market.

Dynamic power density and rising leakage power becoming more problematic at each new node.