tag: 3D stacking

The Future Of ASICS In 3D
By Javier DeLaCruz - 26 May, 2011 - Comments: 0

By Javier DeLaCruz 3D technology is generating a lot of interest as a way to reduce NRE costs and speed time to market. This is still a nascent approach, so people are looking for a single standard in through-silicon vias (TSVs), primarily to reduce infrastructure costs. Unfortunately, I do not think this will be possible. There are at least two fundamentally different applications for 3D t... » read more

Planning For Physical Effects
By Ed Sperling - 06 May, 2011 - Comments: 0

The importance of Intel’s announcement that it has perfected 3D transistors and will roll them out this year should not be understated. This is a major breakthrough technologically, with major implications for power, performance and even competitiveness. FinFETs have been the subject of some intensive research for more than a decade, with the University of California at Berkeley leading the c... » read more

Experts At The Table: Yield Issues
By Ed Sperling - 22 Apr, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield with Amiad Conley, technology marketing manager for yield and process control at Applied Materials; Cyrus Tabery, senior member of the GlobalFoundries technical staff for lithography development and DFM; Brady Benware, engineering manager for diagnosis and yield at Mentor Graphics, and Ankush Oberai, general man... » read more

Behind The Analog Frenzy
By Ed Sperling - 08 Apr, 2011 - Comments: 0

Analog is suddenly very hot again, and much of it appears to be due to the promise of 2.5D and 3D stacking. Texas Instruments pulled out its checkbook to pay $6.5 billion for National Semiconductor, and Microsemi has offered $28 million for AML Communications, which makes low-noise and high-power microwave amplifiers. So what’s behind these move? In TI’s case, there appears to be a re... » read more

The Shocking Side Of 3D
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ann Steffora Mutschler The pesky static charge that builds up on your clothing when you forget the dryer sheet is more than just a nuisance when it comes to manufacturing ICs. Add 3D structures and process scaling to the mix and the challenge of adequately protecting those devices grows significantly. While this problem used to be largely an afterthought, the charged-device model type of... » read more

Experts At The Table: 3D Stacking
By Ed Sperling - 25 Feb, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice pr... » read more

Experts At The Table: 3D Stacking
By Ed Sperling - 14 Feb, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice pre... » read more

Moore’s Law Will Never End
By Ed Sperling - 17 Dec, 2010 - Comments: 0

Moore’s Law has been many things to many people. It has been a statement of physical limits and an economic formula. It has been the cause of overheating and complex power solutions, and it has been a competitive weapon among companies looking to boost performance and cut costs. It also has been revised on more than one occasion as the time frame in which the number of transistors doubles ... » read more

Experts At The Table: IP Integration Hurdles
By Ed Sperling - 17 Dec, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss IP integration issues with Ken Brock, senior staff product marketing manager for logic libraries in Synopsys’ Solutions Group; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversati... » read more

New 3D Stacking Techniques Emerge
By Ed Sperling - 16 Dec, 2010 - Comments: 0

By Pallab Chatterjee To take advantage of the capabilities of the new technologies, design and circuit architectures in the future will have to be closely coupled with the basic device creation. That shift was the subject of a special session at the recent IEDM conference focusing on the confluence of technology and design. One such area under discussion involved 3D ICs. While a lot of disc... » read more

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