tag: 3D stacking

Experts At The Table: IP Integration Hurdles
By Ed Sperling - 17 Dec, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss IP integration issues with Ken Brock, senior staff product marketing manager for logic libraries in Synopsys’ Solutions Group; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversati... » read more

New 3D Stacking Techniques Emerge
By Ed Sperling - 16 Dec, 2010 - Comments: 0

By Pallab Chatterjee To take advantage of the capabilities of the new technologies, design and circuit architectures in the future will have to be closely coupled with the basic device creation. That shift was the subject of a special session at the recent IEDM conference focusing on the confluence of technology and design. One such area under discussion involved 3D ICs. While a lot of disc... » read more

Beyond 22nm
By Ed Sperling - 15 Dec, 2010 - Comments: 0

Gary Patton, VP at IBM's semiconductor R&D Center, talks with System-Level Design about the challenges of developing chips all the way down to 15nm. [youtube vid=2wTj3EvRIRw]   » read more

3D Stacked Die Create Unique Test Issues
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler While 3D die stacking promises a number of benefits including smaller footprint, faster speed, lower power and possibly lower cost, testing those devices isn’t going to be simple. There are varying degrees of challenges aligned with varying types of defects that occur throughout the process, from wafer fabrication to package assembly to system-level assembly. And... » read more

The Growing Legacy Of Moore’s Law
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ed Sperling Moore’s Law has defined semiconductor design since it was introduced in 1965, but increasingly it also has begun defining the manufacturing equipment, the cooling needed for end devices, and both the heat and performance of systems. In the equipment sector the big problem has been the delay in rolling out extreme ultraviolet (EUV). Moore’s Law will require tighter spacing... » read more

The Future Of 3D Stacking
By Ed Sperling - 21 Oct, 2010 - Comments: 0

By Ed Sperling Despite concerns about the lack of tools, an unstable process, questionable interconnects, thermal overloads and electrostatic discharge, 3D stacking appears to be making headway. At the very least, lots of companies of all sizes are betting heavily that it will succeed. The first wave, which is expected to start showing up late next year, will likely come from a handful of t... » read more

Turn Up The Heat
By Ed Sperling - 15 Oct, 2010 - Comments: 0

For the better part of two years talk of 3D stacking has been filled with concerns about thermal issues. If you stack logic on logic or memory on memory or CPU on CPU, the chance of causing a fatal failure in the circuitry was assumed to be very high. It turns out that may not be the case after all. Companies working with early prototypes of 3D stacks say silicon itself may be one of the bes... » read more

Betting On 3D
By Ed Sperling - 26 Aug, 2010 - Comments: 0

The continuation of Moore’s Law appears less in doubt than ever. Companies such as Intel, ST, AMD (via GlobalFoundries) and IBM are testing FinFETS and ETSOI and work is being done on the back end to ensure that these new structures can be manufactured with sufficient yield. What’s changed, though, is the resistance by other companies to the progression of Moore’s Law. There is no long... » read more

Stressing Over 3D
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By David Lammers Pol Marchal recalls putting a stacked 3D prototype on his desk at IMEC in Leuven, Belgium, last year, which a visitor picked up and examined two months later. “I don’t think this chip will work,” the visitor said, causing Marchal, principal scientist at IMEC’s 3D system integration program, to put the stacked die under a microscope. Sure enough, Pol found that mechanic... » read more

The Great Divide
By Ed Sperling - 27 May, 2010 - Comments: 0

By Ed Sperling One size no longer fits all, and that’s causing consternation across the supply chain from established EDA vendors to point tool developers all the way up to the largest chipmakers. While the overall number of design starts for SoCs really hasn’t changed much, despite a drop in the number of companies working at the most advanced process nodes, what has changed significan... » read more

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