tag: ARM

Experts At The Table: The Trouble With Corners
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss corners with PV Srinivas, senior director of engineering at Mentor Graphics; Dipesh Patel, vice president of engineering for physical IP at ARM; Lisa Minwell, director of technical marketing at Virage Logic; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversation. LPE: Corners appears to be get... » read more

ESL Requires New Approaches To Design And Verification
By Ann Mutschler - 22 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler As more data gets front loaded into SoC architectures today, understanding verification challenges as well as communication between the front and back end has never been more critical. “All of this is getting more complicated,” said John Ford, director of marketing at ARM. “There was a time when an ARM processor core was all that was on a chip. Now there’s ... » read more

‘Good’ Vs. ‘Good Enough’
By Ed Sperling - 22 Jul, 2010 - Comments: 0

By Ed Sperling The decision for when a chip is ready for tapeout is changing—both in time and sometimes in terms of who’s actually making that decision—as the amount of software being developed by hardware companies continues to grow. At the root of this shift are two very different concepts about what constitutes a market-ready product. For SoC engineers, fixing bugs after a chip has... » read more

Smarter Video Chips, Smarter Business Model
By Ed Sperling - 21 Jul, 2010 - Comments: 0

Pixim's CEO talks about what the company outsources, what it keeps internal, and how it differentiates from the competition. [youtube vid=jDoaQ91QM3c] » read more

The Power Of IP
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler As the number of design starts goes down the corresponding complexity of SoCs has gone up—and continues to grow. Everyone is looking at the value they can bring to the table as increasing proportions of SoCs are either reused from pre-existing IP within the company designing the chip or brought in from outside. Because is economically impractical to start an SoC... » read more

Keeping Models In Sync
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ed Sperling Models and higher levels of abstraction have been hailed as the best choice for developing SoCs at advanced process nodes, but at 28nm and beyond even that approach is showing signs of stress. The number of models needed for a complex SoC has been growing at each new process node, which makes it much more difficult to keep them updated and in sync as the design progresses down t... » read more

Connecting The Pieces
By Ann Mutschler - 24 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler With the amount of IP blocks being integrated in SoCs today – in some cases as many as 100 blocks in a single chip – SoC design methodologies are shifting to address the new challenges this complexity brings. The good news is that these integration challenges has put the spotlight on the issues—along with the skyrocketing development costs for the creation, qual... » read more

The Future Of IP
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By Ed Sperling The rapid consolidation of the IP business is raising big questions about who will be left, whether new companies will join, and what it means for chipmakers looking to buy IP. In a period of one month Synopsys bought Virage Logic, which had just finished a buying spree of its own with the acquisitions of ARC and the IP business of NXP, and Cadence bought Denali. So what exac... » read more

Synopsys Plus Virage: Combinatorics Or Common Sense?
By Jack Harding - 24 Jun, 2010 - Comments: 0

By Jack Harding It should be no surprise. The industry has been consolidating and expanding and consolidating for nearly 40 years. So when Virage Logic was gobbled up by Synopsys and Denali was ingested by Cadence, it is really a lot more of the same. Or is it? There is a difference. Synopsys has made it crystal clear that its definition of EDA now permanently includes IP. Not that acquirin... » read more

Special Report: Using FPGAs For 3D Stacking
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Xilinx is developing a 3D architecture for its FPGAs and Actel has been approached by SoC makers to use its flash-based FPGA as a layer in a 3D IC stack. Both approaches could radically alter the fundamental equation about the tradeoffs between FPGAs and ASICs—particularly the power and performance overhead normally associated with programmable logic. Xilinx declined to com... » read more

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