Week In Review: Design, Low Power

By Jesse Allen - 17 Mar, 2023 - Comments: 0

The UK government published its National Quantum Strategy, which outlines the plan to invest £2.5 billion (~$3.0 billion) over the next 10 years into quantum technology, including computing, sensing, timing, imaging, and networking. "We will develop UK strengths across different hardware platforms, software, and components, and reinforce our capabilities throughout the supply chains. Although ... » read more

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing

By eBeam Initiative - 15 Mar, 2023 - Comments: 0

Published by the eBeam Initiative Member Companies (February 2023), this list of artificial intelligence (AI) systems used by member companies in their semiconductor manufacturing products shows progress. New examples of systems using AI include: image processing and parameter tuning in lithography tool mask metrology system B-SPline Control Point generation tool sem... » read more

Chip Industry’s Technical Paper Roundup: Dec. 13

By Linda Christensen - 13 Dec, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week.[table id=70 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us po... » read more

New Method to Measure, At The Wafer Scale, Direct Bonding Energies (CEA-LETI)

By Technical Paper Link - 12 Dec, 2022 - Comments: 0

A new technical paper titled "Double cantilever beam bonding energy measurement using confocal IR microscopy" was published by researchers at Univ. Grenoble Alpes, CEA-LETI and SOITEC, Parc Technologique des Fontaines. "A new technique is assessed in order to measure, at the wafer scale, direct bonding energies. It is derived from the standard Double Cantilever Beam (DCB) method and uses int... » read more

Week In Review: Manufacturing, Test

By Karen Heyman - 09 Dec, 2022 - Comments: 2

The more than 1,400 attendees at this week’s IEDM, which celebrated the 75th anniversary of the transistor, were clearly focused on making the next 75 years of semiconductors even more remarkable than the last. Intel, Samsung, TSMC, STMicroelectronics, GlobalFoundries and imec announced breakthrough devices, materials, and even integration approaches. These included: Intel showcased adva... » read more

Week In Review: Design, Low Power

By Jesse Allen - 09 Dec, 2022 - Comments: 0

Tools, IP, design Codasip launched a new organization within the company to support the development and commercialization of technical innovations in key applications including security, functional safety, and AI/ML. "As semiconductor scaling is showing its limits, there is an obvious need for new ways of thinking. We will be working with universities, research institutes and strategic partner... » read more

Chip Industry’s Technical Paper Roundup: Nov. 15

By Linda Christensen - 15 Nov, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=63 /] » read more

Using More Germanium In Chips for Energy Efficiency & Achievable Clock Frequencies

By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Composition Dependent Electrical Transport in Si1−xGex Nanosheets with Monolithic Single-Elementary Al Contacts" was published by researchers at TU Wien (Vienna University of Technology), Johannes Kepler University, CEA-LETI, and Swiss Federal Laboratories for Materials Science and Technology. Find the technical paper here. Published September 2022. Abstrac... » read more

Legacy Tools, New Tricks: Optical 3D Inspection

By Karen Heyman - 08 Nov, 2022 - Comments: 0

Stacking chips is making it far more difficult to find existing and latent defects, and to check for things like die shift, leftover particles from other processes, co-planarity of bumps, and adhesion of different materials such as dielectrics. There are several main problems: Not everything is visible from a single angle, particularly when vertical structures are used; Various struc... » read more

Hybrid Bonding Moves Into The Fast Lane

By Laura Peters - 21 Jul, 2022 - Comments: 1

The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

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tag: CEA-Leti

Week In Review: Design, Low Power

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing

Chip Industry’s Technical Paper Roundup: Dec. 13

New Method to Measure, At The Wafer Scale, Direct Bonding Energies (CEA-LETI)

Week In Review: Manufacturing, Test

Week In Review: Design, Low Power

Chip Industry’s Technical Paper Roundup: Nov. 15

Using More Germanium In Chips for Energy Efficiency & Achievable Clock Frequencies

Legacy Tools, New Tricks: Optical 3D Inspection

Hybrid Bonding Moves Into The Fast Lane

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