tag: chip design

The Growing Uncertainty Of Sign-Off At 7/5nm
By Ann Mutschler - 09 May, 2019 - Comments: 3

Having enough confidence in designs to sign off prior to manufacturing is becoming far more difficult at 7/5nm. It is taking longer due to increasing transistor density, thinner gate oxides, and many more power-related operations that can disrupt signal integrity and impact reliability.  For many years, designers have performed design rule checks as part of physical verification of the desi... » read more

Raising The Abstraction Level For Power
By Brian Bailey - 09 May, 2019 - Comments: 0

Power-aware design is still a relatively new concern for many semiconductor products, and since inception it has changed several times and in different ways. Initially people were concerned about peak power. Today, they care about peak, total energy, thermal and other effects. The industry has tried several abstractions ranging from system-level analysis, which promised to swamp implementati... » read more

The Rising Importance Of Design Planning
By Jim Schultz - 09 May, 2019 - Comments: 0

Design Planning is often overlooked in the chip design flow. The front-end designer carefully architects the design functionality to produce golden RTL. This is then poured into the synthesis engine to produce logic gates. The synthesized netlist is then thrown over the wall by the front-end designer for physical implementation. The back-end designer receives a gate-level netlist, timing con... » read more

Selecting A Portable Stimulus Application Focal Point
By Mentor, a Siemens Business - 08 May, 2019 - Comments: 0

The "axes of reuse" are a powerful way to identify a focal point for your application of Portable Stimulus. Picking a focal point helps to identify needed resources and identify the gap between what is needed and what already exists in your organization. Picking an initial focal point for applying Portable Stimulus doesn’t preclude expanding the application of Portable Stimulus in the future.... » read more

DAC: An Exhibitor’s Perspective
By Diana Dearin - 08 May, 2019 - Comments: 0

It is less than four weeks to DAC. At this point you should be deep into your planning and ready to drop down secure all your exhibit services before the deadline. While you are thinking about how to manage all the details of getting your booth on the show floor, this is a great time to take a step back and make sure you have clearly defined exhibit “takeaways” — think “goals” and ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Apr, 2019 - Comments: 0

A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog a... » read more

The Case For Embedded FPGAs Strengthens And Widens
By Brian Bailey - 25 Apr, 2019 - Comments: 2

The embedded FPGA, an IP core integrated into an ASIC or SoC, is winning converts. System architects are starting to see the benefits of eFPGAs, which offer the flexibility of programmable logic without the cost of FPGAs. Programmable logic is especially appealing for accelerating machine learning applications that need frequent updates. An eFPGA can provide some architects the cover they ne... » read more

Week In Review: Design, Low Power
By Jesse Allen - 19 Apr, 2019 - Comments: 0

Intel acquired vision and video FPGA IP company Omnitek. Founded in 1998, the Basingstoke, England-based company has produced FPGA IP cores for video processing including conversion and enhancement, creating arbitrary image warps on a real time video stream, connectivity, and deep learning and AI inferencing. Terms of the deal were not disclosed. Qualcomm and Apple have dropped all litigatio... » read more

Blog Review: April 17
By Jesse Allen - 17 Apr, 2019 - Comments: 0

In a video, Mentor's Colin Walls digs into power management in embedded software with a particular look at the Power Pyramid model. Synopsys' Taylor Armerding checks out the state of application security at this year's RSA and finds that while organizations are paying attention to security through training and dedicated teams, roadblocks still remain. Cadence's Paul McLellan considers how... » read more

Target: 50% Reduction In Memory Power
By Brian Bailey - 11 Apr, 2019 - Comments: 3

Memory consumes about 50% or more of the area and about 50% of the power of an SoC, and those percentages are likely to increase. The problem is that static random access memory (SRAM) has not scaled in accordance with Moore's Law, and that will not change. In addition, with many devices not chasing the latest node and with power becoming an increasing concern, the industry must find ways to... » read more

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