tag: CoWoS

GUC GLink Test Chip Uses In-Chip Monitoring And Deep Data Analytics For High Bandwidth Die-To-Die Characterization
By proteanTecs - 11 Oct, 2022 - Comments: 0

Advanced ASIC leader Global Unichip Corp (GUC) has developed GLink, a high-bandwidth, low-latency, and power-efficient die-to-die (D2D) interface. GLink offers the industry’s highest optimized interconnect solution for both CoWoS and InFO packaging technologies. The GUC and proteanTecs collaboration started with GUC’s second generation of GLink, known as GLink 2.0. The project target was... » read more

Advancing 3D Integration
By Paul McLellan - 10 Jun, 2021 - Comments: 0

Jerry Tzou's recent presentation on 3D Fabric Technology was all about More than Moore. TSMC has other specialized technologies such as RF and eNVM, but this is a general foundational technology for hyperscale data centers, mobile, and AI. Jerry started with the motivation for using chiplets and heterogeneous chip integration. You can see in the diagram below on the left where die from node... » read more

Many Chiplet Challenges Ahead
By Brian Bailey - 12 Apr, 2021 - Comments: 0

Over the past couple of months, Semiconductor Engineering has looked into several aspects of 2.5D and 3D system design, the emerging standards and steps that the industry is taking to make this more broadly adopted. This final article focuses on the potential problems and what remains to be addressed before the technology becomes sustainable to the mass market. Advanced packaging is seen as ... » read more

Designing 2.5D Systems
By Brian Bailey - 15 Mar, 2021 - Comments: 0

As more designs hit the reticle limit, or suffer from decreasing yield, migrating to 2.5D designs may provide a path forward. But this kind of advanced packaging also comes with some additional challenges. How you adapt and change your design team may be determined by where your focus has been in the past, or what you are trying to achieve. There are business, organizational, and technical c... » read more

Surviving The Three Phases Of High Density Advanced Packaging Design
By Siemens EDA - 24 Feb, 2021 - Comments: 0

The growth of High Density Advanced Packages (HDAP) such as FOWLP, CoWoS, and WoW is triggering a convergence of the traditional IC design and IC package-design worlds. To handle these various substrate scenarios, process transformation must occur. This paper discusses the three phases of HDAP design and provides tips on how to survive their challenges. To read more, click here. » read more

Ensuring HBM Reliability
By Ed Sperling - 27 May, 2020 - Comments: 0

Igor Elkanovich, CTO of GUC, and Evelyn Landman, CTO of proteanTecs, talk with Semiconductor Engineering about difficulties that crop up in advanced packaging, what’s redundant and what is not when using high-bandwidth memory, and how continuous in-circuit monitoring can identify potential problems before they happen. » read more

Reliability Monitoring Of GUC 7nm High-Bandwidth Memory (HBM) Subsystem
By proteanTecs - 27 Apr, 2020 - Comments: 0

This white paper presents the use of proteanTecs’ Proteus for HBM subsystem reliability based on deep data analytics and enhanced visibility, overcoming the limitations of advanced heterogeneous packaging. It will describe the operation concept and provide results from a GUC 7nm HBM Controller ASIC. A typical CoWoS chip has hundreds of thousands of micro-bumps (u-bumps). 3-8 u-bumps are us... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 06 Mar, 2020 - Comments: 0

Fab tools, materials and packaging Intel has recognized 37 companies for its annual suppliers’ awards. The list includes equipment, materials, packaging houses and other segments. These suppliers have collaborated with Intel to implement process improvements with good products and services. See who made the list here. ---------------------------------------- Lam Research has introduced... » read more

Electromagnetic Challenges In High-Speed Designs
By Ed Sperling - 25 Nov, 2019 - Comments: 0

ANSYS’ Anand Raman, senior director, and Nermin Selimovic, product sales specialist, talk with Semiconductor Engineering about how to deal with rising complexity and tighter tolerances in AI, 5G, high-speed SerDes and other chips developed at the latest process nodes where the emphasis is on high performance and low power. » read more

EDA Gears Up For 3D
By Brian Bailey - 26 Aug, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor Business Unit of ANSYS; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Bus... » read more

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