tag: CTE

Managing Wafer Retest
By Anne Meixner - 19 May, 2021 - Comments: 1

Every wafer test touch-down requires a balance between a good electrical contact and preventing damage to the wafer and probe card. Done wrong, it can ruin a wafer and the customized probe card and result in poor yield, as well as failures in the field. Achieving this balance requires good wafer probing process procedures as well as monitoring of the resulting process parameters, much of it ... » read more

Designing 2.5D Systems
By Brian Bailey - 15 Mar, 2021 - Comments: 0

As more designs hit the reticle limit, or suffer from decreasing yield, migrating to 2.5D designs may provide a path forward. But this kind of advanced packaging also comes with some additional challenges. How you adapt and change your design team may be determined by where your focus has been in the past, or what you are trying to achieve. There are business, organizational, and technical c... » read more

Die-To-Die Stress Becomes A Major Issue
By Ann Mutschler - 14 Jan, 2021 - Comments: 2

Stress is becoming more critical to identify and plan for at advanced nodes and in advanced packages, where a simple mismatch can impact performance, power, and the reliability of a device throughout its projected lifetime. In the past, the chip, package, and board in a system generally were designed separately and connected through interfaces from the die to the package, and from the packag... » read more

Challenges And Approaches To Developing Automotive Grade 1/0 FCBGA Package Capability
By Amkor - 18 Nov, 2020 - Comments: 0

Automotive Grade 1 and 0 package requirements, defined by Automotive Electronics Council (AEC) Document AEC-100, require more severe temperature cycling and high temperature storage conditions to meet harsh automotive field requirements, such as a maximum 150°C device operating temperature, 15-year reliability and zero-defect quality level. Moreover, increased integration of device functionali... » read more

3nm: Blurring Lines Between SoCs, PCBs And Packages
By Ann Mutschler - 02 Mar, 2020 - Comments: 5

Leading-edge chipmakers, foundries and EDA companies are pushing into 3nm and beyond, and they are encountering a long list of challenges that raise questions about whether the entire system needs to be shrunk onto a chip or into a package. For 7nm and 5nm, the problems are well understood. In fact, 5nm appears to be more of an evolution from 7nm than a major shift in direction. But at 3nm, ... » read more

Using Digital Image Correlation To Determine BGA Warpage
By Craig Hillman - 16 Jan, 2020 - Comments: 0

Digital image correlation (DIC) is a non-contact, full-field displacement, optical measurement technique. It is often used in the following applications: Material characterization Coefficient of thermal expansion (CTE) Glass transition temperature Young’s modulus Poisson’s ratio Sample testing for fatigue and failure In situ monitoring of displacements and str... » read more

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