I Just Want Closure!

By Jean-Marie Brunet - 15 Aug, 2013 - Comments: 0

By Jean-Marie Brunet We all know it by now, but let’s say it one more time for the cameras—the level of complexity of closure at 20 nm and below is considerably higher than for any previous nodes. While the migration of manufacturing requirements into design started with a few suggested activities at 65 nm, such as recommended rules compliance, lithography checks, and critical area analysi... » read more

It’s A Materials World

By Mark LaPedus - 15 Aug, 2013 - Comments: 0

By Mark LaPedus At a recent event, Intel’s fab materials guru described a nightmarish occurrence that nearly brought the chip giant to its knees. Tim Hendry, director of fab materials and vice president of the Technology and Manufacturing Group at Intel, said the company obtained a critical material from an undisclosed supplier. “This large sub-supplier, a very large chemical company, m... » read more

The Week In Review: July 12

By Ed Sperling - 12 Jul, 2013 - Comments: 0

By Ed Sperling Cadence rolled a new version of its layout suite of tools for electrically aware designs, allowing design teams to check on electrical issues while the layout is being done. The company says this can reduce circuit design time by up to 30%, in addition to optimizing for performance and area. Cadence also announced a deal with Global Unichip, which successfully taped out a 20nm ... » read more

Let’s All Meet At The Via Bar!

By Jean-Marie Brunet - 30 Jun, 2013 - Comments: 0

By Jean-Marie Brunet At 28 nm and below, a variety of new design requirements are forcing us to adjust the traditional layout and verification process of digital designs. The use of vias, in particular, has been significantly impacted. New via types have been introduced, and the addition of double patterning, FinFETS, and other new design techniques has not only generated a considerable increa... » read more

DFM Success At SMIC

By Mentor, a Siemens Business - 28 May, 2013 - Comments: 0

Jeff Wilson As any integrated circuit (IC) designer knows, design rules are the “first line of defense” foundries provide in the effort to ensure all IC designs are ultimately manufacturable. Coming in a close second, design for manufacturing (DFM) rules enable designers to maximize design capabilities and performance while minimizing or optimizing the use of chip space. At today’s ad... » read more

Chasing Rabbits

By David Abercrombie - 21 Mar, 2013 - Comments: 0

“Now, here, you see, it takes all the running you can do, to keep in the same place. If you want to get somewhere else, you must run at least twice as fast as that!” —Lewis Carroll, Through the Looking Glass By David Abercrombie As I discussed in my previous article, the use of stitching can greatly reduce the number of double patterning (DP) decomposition violations that a designer ... » read more

Breakthroughs Required

By Ed Sperling - 21 Mar, 2013 - Comments: 0

Linear progressions have a hypnotic effect on even the smartest people. They lull everyone into thinking that progress—or at least a progression—is a straight line, with little or no recognition that things are changing around the edges. The periphery is definitely changing, though. And over the next couple of process nodes, the semiconductor manufacturing industry either will have to fi... » read more

Making The Right Choices

By Ed Sperling - 21 Feb, 2013 - Comments: 0

FD-SOI at 28nm, or finFETs at 20/14nm? To companies looking at the cost equation, the total market opportunity for SoCs and the NRE required to get there, this is still a manageable formula. It requires lots of number crunching and some unknowns, but by the time you get done with the math it still falls within an acceptable margin of error and the choices are relatively simple. For foundries... » read more

Uncommon Goals

By Atrenta - 14 Feb, 2013 - Comments: 0

I had the opportunity to attend the Common Platform event recently. This is a technology and business showcase sponsored by Global Foundries, IBM and Samsung with major support from ARM, Cadence, Synopsys and Mentor. Wow, that’s some serious sponsorship. The event was well run and provided a good balance of technology details and business outlook. The wine at the evening reception was decent ... » read more

Reducing The Drama In DFM

By Ed Sperling - 24 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler For reducing cycle time of DFM checks prior to manufacturing, pattern matching is a topic of great excitement as of the past few manufacturing nodes. The idea behind the technology is that there are certain patterns in the physical layout of the chip, which unless they are addressed, won’t come out right. That’s what causes the drama, observed Saleem Haider, se... » read more

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Knowledge Centers
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eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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