Verifying Your Intent

By Ann Mutschler - 21 Mar, 2013 - Comments: 0

Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before manufacturing. Checking electrical characteristics of a design is one thing. Verifying power intent is quite another. And the overlap of the two is an intriguing concept. Case in point: Checking fo... » read more

Reducing IC Cycle Time With Calibre

By Various Writers - 15 Nov, 2012 - Comments: 0

Technology is both a blessing and a curse. The same shrinking of transistor size that has enabled chip designers to place significantly more functionality on the same die area is also responsible for the significant increases we have seen in the number and complexity of verification rules. It would be nice if we could use this phenomenon to our advantage, as an excuse for why our job of physica... » read more

Challenges Of Physical Design Closure

By Jean-Marie Brunet - 22 Oct, 2012 - Comments: 0

By Jean-Marie Brunet A clear trend in IC design is that with each smaller process node, reaching design closure gets more difficult, expensive, and time consuming. Printing ever-smaller features with 193nm wavelength light has introduced unprecedented levels of manufacturing challenges, which are addressed with a growing set of complex design rules (DRC) and design for manufacturing (DFM) cons... » read more

Experts At The Table: Challenges At 20nm

By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the challenges at 20nm and beyond with Jean-Pierre Geronimi, special projects director at STMicroelectronics; Pete McCrorie, director of product marketing for silicon realization at Cadence; Carey Robertson, director of product marketing at Mentor Graphics; and Isadore Katz, president and CEO of CLK Design Automation. Wh... » read more

Fill Challenge Solved: Why SmartFill is as Good as it Sounds

By Jean-Marie Brunet - 12 Jan, 2012 - Comments: 0

by Jean-Marie Brunet Among the many steps involved with chip design, there is one known by the deceptively simple name of “fill.” Fill involves adding shapes or polygons to the design that are structural, not logical. That is, they ensure manufacturability by making sure each layer (metal, poly, diffusion) has a proscribed density. As easy as this sounds, fill can be tricky, and the fill... » read more

DFM is a Competitive Weapon

By Mentor Graphics Staff Writers - 01 Nov, 2011 - Comments: 0

By Joe Davis, Mentor Graphics As my mom always told me, you always have a choice. The trick was, you had to be willing to accept the consequences of your decision. Don’t want to clean your room? Okay, but you can’t go out to play until you do. Easy enough to do the analysis on that one when you’re ten years old. But sometimes, understanding the consequences gets a little tougher, an... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer