tag: fan-out

A Production-Worthy Fan-Out Solution — ASE FOCoS Chip Last
By ASE - 16 Dec, 2020 - Comments: 0

The 5th Generation (5G) wireless systems popularity will push the package development into a high performance and heterogeneous integration form. For high I/O density and high performance packages, the promising Fan Out Chip on Substrate (FOCoS) provides a solution to match outsourced semiconductor assembly and testing (OSAT) capability. FOCoS is identified the Fan Out (FO) package, which can f... » read more

Predicting Reliability At 3/2nm And Beyond
By Ed Sperling - 08 Dec, 2020 - Comments: 0

The chip industry is determined to manufacture semiconductors at 3/2nm — and maybe even beyond — but it's unlikely those chips will be the complex all-in-one SoCs that have defined advanced electronics over the past decade or so. Instead, they likely will be one of many tiles in a system that define different functions, the most important of which are highly specialized for a particular app... » read more

LDFO SiP For Wearables & IoT With Heterogeneous Integration
By Amkor - 02 Dec, 2020 - Comments: 0

Authors A. Martins*, M. Pinheiro*, A. F. Ferreira*, R. Almeida*, F. Matos*, J. Oliveira*, Eoin O´Toole*, H. M. Santos†, M. C. Monteiro‡, H. Gamboa‡, R. P. Silva* ‡Fraunhofer Portugal AICOS, Porto, Portugal †INESC TEC *AMKOR Technology Portugal, S.A. ABSTRACT The development of Low-Density Fan-Out (LDFO), formerly Wafer Level Fan-Out (WLFO), platforms to encompass the require... » read more

Momentum Builds For Advanced Packaging
By Mark LaPedus - 17 Sep, 2020 - Comments: 0

The semiconductor industry is stepping up its efforts in advanced packaging, an approach that is becoming more widespread with new and complex chip designs. Foundries, OSATs and others are rolling out the next wave of advanced packaging technologies, such as 2.5D/3D, chiplets and fan-out, and they are developing more exotic packaging technologies that promise to improve performance, reduce p... » read more

Chiplet Momentum Rising
By Mark LaPedus - 26 Feb, 2020 - Comments: 0

The chiplet model is gaining momentum as an alternative to developing monolithic ASIC designs, which are becoming more complex and expensive at each node. Several companies and industry groups are rallying around the chiplet model, including AMD, Intel and TSMC. In addition, there is a new U.S. Department of Defense (DoD) initiative. The goal is to speed up time to market and reduce the cost... » read more

Finding Defects In IC Packages
By Mark LaPedus - 17 Dec, 2019 - Comments: 0

Several equipment makers are ramping up new inspection equipment to address the growing defect challenges in IC packaging. At one time, finding defects in packaging was relatively straightforward. But as packaging becomes more complex, and as it is used in markets where reliability is critical, finding defects is both more difficult and more important. This has prompted the development of a ... » read more

New Packaging Roadmap
By Katherine Derbyshire - 17 Dec, 2019 - Comments: 3

Historically, the electronics industry has drawn sharp distinctions between the integrated circuit chip, the package that protects it from the environment, and the board that connects it to other devices in a complete system. The circuit and systems worlds have been largely isolated from each other, using different tools, different processes, and different metrics for success. While integrated ... » read more

What’s Next For High Bandwidth Memory
By Mark LaPedus - 17 Dec, 2019 - Comments: 1

A surge in data is driving the need for new IC package types with more and faster memory in high-end systems. But there are a multitude of challenges on the memory, packaging and other fronts. In systems, for example, data moves back and forth between the processor and DRAM, which is the main memory for most chips. But at times this exchange causes latency and power consumption, sometimes re... » read more

Migrating 3D Into The Mainstream
By Brian Bailey - 31 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for ANSYS' Semiconductor Business Unit; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Business;... » read more

What’s The Best Advanced Packaging Option?
By Mark LaPedus - 17 Oct, 2019 - Comments: 2

As traditional chip designs become more unwieldy and expensive at each node, many IC vendors are exploring or pursuing alternative approaches using advanced packaging. The problem is there are too many advanced packaging options on the table already, and the list continues to grow. Moreover, each option has several tradeoffs and challenges, and all of them are still relatively expensive. ... » read more

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