tag: fan-out

Week In Review: Manufacturing, Test
By Mark LaPedus - 04 Oct, 2019 - Comments: 0

Packaging and test In a major deal that has some implications in the OSAT supply chain, South Korea’s Nepes has taken over Deca Technologies’ wafer-level packaging manufacturing line in the Philippines. In addition, Nepes has also licensed Deca’s M-Series wafer-level packaging technology. This includes fan-in technology as well as wafer- and panel-level fan-out. It also includes an ad... » read more

The Race To Next-Gen 2.5D/3D Packages
By Mark LaPedus - 23 Sep, 2019 - Comments: 4

Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing future packages based on one emerging interconnect scheme, called copper-to-copper hybrid bonding. This technology provides a way to stack advanced dies using copper connections at the chip level,... » read more

Advanced Packaging Options Increase
By Ed Sperling - 19 Aug, 2019 - Comments: 0

Designing, integrating and assembling heterogeneous packages from blocks developed at any process node or cost point is proving to be far more difficult than expected, particularly where high performance is one of the main criteria. At least part of the problem is there is a spectrum of choices, which makes it hard to achieve economies of scale. Even where there is momentum for a particular ... » read more

Cloudy Outlook Seen For IC Biz
By Mark LaPedus - 29 Jul, 2019 - Comments: 0

After a slowdown in the first half of 2019, chipmakers and equipment vendors face a cloudy outlook for the second half of this year, with a possible recovery in 2020. Generally, the semiconductor industry began to see a slowdown starting in mid- to late-2018, which extended into the first half of 2019. During the first half of this year, memory and non-memory vendors were negatively impacted... » read more

Challenges Grow For 5G Packages And Modules
By Mark LaPedus - 18 Jul, 2019 - Comments: 0

The shift to 5G wireless networks is driving a need for new IC packages and modules in smartphones and other systems, but this move is turning out to be harder than it looks. For one thing, the IC packages and RF modules for 5G phones are more complex and expensive than today's devices, and that gap will grow significantly in the second phase of 5G. In addition, 5G devices will require an as... » read more

Manufacturing Bits: June 25
By Mark LaPedus - 25 Jun, 2019 - Comments: 0

Panel-level consortium Fraunhofer is moving forward with the next phase of its consortium to develop technologies for panel-level packaging. In 2016, Fraunhofer launched the original effort, dubbed the Panel Level Packaging Consortium. The consortium, which had 17 partners, developed various equipment and materials in the arena. Several test layouts were designed for process development on ... » read more

Sidestepping Moore’s Law
By Mark LaPedus - 20 Jun, 2019 - Comments: 2

Calvin Cheung, vice president of engineering at ASE, sat down with Semiconductor Engineering to talk about advanced packaging, the challenges involved with the technology, and the implications for Moore’s Law. What follows are excerpts of that conversation. SE: What are some of the big issues with IC packaging today? Cheung: Moore’s Law is slowing down, but transistor scaling will co... » read more

Manufacturing Bits: June 18
By Mark LaPedus - 18 Jun, 2019 - Comments: 0

Making microvias in packages At the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas, Georgia Institute of Technology, Tokyo Ohka Kogyo (TOK) and Panasonic presented a paper on a technology that enables ultra-small microvias for advanced IC packages. Researchers demonstrated a picosecond UV laser technology as well as materials, which enabled 2μm to 7μm vias... » read more

Manufacturing Bits: June 10
By Mark LaPedus - 10 Jun, 2019 - Comments: 1

Predicting warpage in packages At the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas, there were several papers on ways to predict variation and warpage in IC packages. Advanced packages are prone to unwanted warpage during the process flow. The warpage challenges escalate as the packages become thinner. Warpage in turn can impact yields in IC packages. ... » read more

ECTC Packaging Trends
By Mark LaPedus - 10 Jun, 2019 - Comments: 0

At the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas, a number of packaging houses, R&D organizations and universities presented a slew of papers on the latest IC packaging technologies. The event provided a glimpse of the future of packaging, which is becoming more important in the industry. At one time, IC packaging took a backseat in the semiconductor... » read more

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