tag: finFETs

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: What are ... » read more

Innovative Wafers For Energy-Efficient CMOS Technology
By Various Writers - 18 Oct, 2012 - Comments: 0

For continued attractiveness and competitiveness of advanced electronic appliances such as smartphones, TVs, notebooks or tablets, the semiconductor industry is moving to “fully depleted” transistor technology to build integrated circuits. This technology comes in two flavors: planar and tri-dimensional (FinFET), each with its own advantages and challenges. This White Paper explains how inn... » read more

New Math
By Ed Sperling - 18 Oct, 2012 - Comments: 0

It was nice when we had round numbers to work with. It was pretty simple to move from 180nm to 120nm and then to 90nm. Then the half nodes started—45/40, 32/28 and 22/20nm. After 14nm we are poised dangerously over the single-digit process nodes. Intel is working on 10nm, to be followed by 7nm or 5nm. Other companies are looking at 11nm, to be followed by 8nm, 6nm or something even further... » read more

Experts At The Table: IC Manufacturing Challenges
By Ed Sperling - 01 Oct, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down with Carlos Mazure, chief technical officer at Soitec; Jeff Hebb, vice president of laser product marketing at Ultratech; Markus Wimplinger, corporate technology development and IP director at EV Group; and Girish Dixit, vice president of the customer integration center and process interactions at Lam Research. What follows are ... » read more

Near-Threshold Computing
By Bhanu Kapoor - 13 Sep, 2012 - Comments: 0

By Bhanu Kapoor There were two main contributing factors to power becoming a big problem ("The Power Wall") starting around the 65nm process technology. First, the fast-growing leakage component became as significant as the dynamic power. Second, the scaling of the supply voltage stopped around 1.1 volts. Process technology advances such as HKMG and 3D tri-gate transistors have enabled con... » read more

The Trouble With FinFETs
By Joanne Itow - 16 Aug, 2012 - Comments: 0

By Joanne Itow The industry’s quest to continue on the semiconductor roadmap defined by Moore’s Law has led to the adoption of a new transistor structure. Whether you call them finFETs, tri-gate or 3D transistors, building these new devices is difficult. But the technology is only half the challenge. In 2002, Chen Ming Hu* spoke at the Semico Summit. The title of his presentation was �... » read more

Ivy Bridge Settles Old Bet
By Marc David Levenson - 16 Aug, 2012 - Comments: 0

Think back seven years to 2005. Those were boom times with the housing market rising, the dollar high, 65nm node chips on the horizon and EUV the great future lithography hope. EUVL was late for the next (45nm) node, but a great new idea had appeared to fill the gap—water immersion scanning with 193nm exposure! But how far could wet 193nm lithography go before EUVL or some new thing, such as ... » read more

What Comes After FinFETs?
By Ed Sperling - 16 Aug, 2012 - Comments: 0

By Mark LaPedus The semiconductor industry is currently making a major transition from conventional planar transistors to finFETs starting at 22nm. The question is what’s next? In the lab, IBM, Intel and others have demonstrated the ability to scale finFETs down to 5nm or so. If or when finFETs runs out of steam, there are no less than 18 different next-generation candidates that could o... » read more

Inflection Points
By Ed Sperling - 15 Aug, 2012 - Comments: 0

Semiconductor Manufacturing and Design talks with Paul Boudre, chief operating officer at Soitec, about FinFETs, industry inflection points, the end of life for planar transistors, bulk CMOS vs. SOI, the differences between fully depleted and partially depleted SOI, and the FD-SOI ecosystem. [youtube vid=8ZhfJLkImlk] » read more

More Design Rules Ahead
By Ed Sperling - 25 Jul, 2012 - Comments: 0

By Ed Sperling & Mark LaPedus For those companies that continue to push the limits of feature shrinkage, designs are about to become more difficult, far more expensive—and much more regulated. Two converging factors will force these changes. First, the limits of current 193nm immersion lithography mean companies now must double pattern at 20nm, and potentially quadruple pattern at 14n... » read more

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