tag: IEEE

Manufacturing Bits: Dec. 29
By Mark LaPedus - 29 Dec, 2020 - Comments: 1

Chiplet-based exascale computers At the recent IEEE International Electron Devices Meeting (IEDM), CEA-Leti presented a paper on a 3D chiplet technology that enables exascale-level computing systems. The United States and other nations are working on exascale supercomputers. Today’s supercomputers are measured in floating point operations per second. The world’s fastest supercomputers c... » read more

Week In Review: Design, Low Power
By Jesse Allen - 18 Dec, 2020 - Comments: 0

Tools, Cloud, IP Valtrix Systems updated its STING design verification tool for RISC-V based CPU and SoC implementations. Version 1.9.0 adds support to verify recent changes to the RISC-V user and privilege specifications, including draft versions of the vector and bit manipulation standard extensions. Preliminary support for the draft version of the RISC-V hypervisor extension has also been a... » read more

The Darker Side Of Hybrid Bonding
By Katherine Derbyshire - 17 Dec, 2020 - Comments: 2

With semiconductors, it's often things everyone takes for granted that cause the biggest headaches, and that problem is compounded when something fundamental changes — such as bonding two chips together using a process aimed at maximizing performance. Case in point: CMP for backend of the line metallization in hybrid bonding. While this is a mature process, it doesn't easily translate for ... » read more

Manufacturing Bits: Nov. 25
By Mark LaPedus - 25 Nov, 2020 - Comments: 0

Lidar-on-a-chip At the upcoming IEEE International Electron Devices Meeting (IEDM), Samsung will present a paper on the industry’s first single-chip lidar beam scanner. (Go to this link and then look for paper 7.2, “Single-Chip Beam Scanner with Integrated Light Source for Real-Time Light Detection and Ranging,” J. Lee et al, Samsung.) Lidar, or light imaging, detection, and ranging, ... » read more

Manufacturing Bits: Nov. 17
By Mark LaPedus - 17 Nov, 2020 - Comments: 0

Intel’s gate-all-around FETs At the upcoming IEEE International Electron Devices Meeting (IEDM), Intel is expected to present papers on its efforts to develop gate-all-around transistors. One paper from Intel describes a more conventional gate-all-around transistor technology called a nanosheet FET. Another paper involves a next-generation NMOS-on-PMOS nanoribbon transistor technology. (F... » read more

112G SerDes Reliability
By Ed Sperling - 05 Oct, 2020 - Comments: 0

Priyank Shukla, product marketing manager at Synopsys, digs into 112Gbps SerDes, why it’s important to examine the performance of these devices in the context of a system, what is acceptable channel loss, and how density can affect performance, power and noise. » read more

The Next Leap
By Ed Sperling - 14 Aug, 2020 - Comments: 0

Some interesting new technologies are about to go on display. Chipmakers and systems companies have been working on quantum computing, photonics, and specialized AI processors, for the past several years, and those efforts are beginning to gain momentum. The goal is no longer a doubling of performance and power. It's now orders of magnitude improvement, and next week's Hot Chips conference i... » read more

Problems And Solutions In Analog Design
By Ann Mutschler - 05 Aug, 2020 - Comments: 1

Advanced chip design is becoming a great equalizer for analog and digital at each new node. Analog IP has more digital circuitry, and digital designs are more susceptible to kinds of noise and signal disruption that have plagued analog designs for years. This is making the design, test and packaging of SoCs much more complicated. Analog components cause the most chip production test failures... » read more

Open-Source Verification
By Brian Bailey - 30 Jul, 2020 - Comments: 1

Ask different people what open-source verification means and you will get a host of different answers. They range from the verification of open-source hardware, to providing an open-source verification infrastructure, to providing open-source stream generators or reference models, to open-source simulators and formal verification engines. Verification is about reducing risk. "Verification is... » read more

What’s After 5G
By Bryon Moyer - 20 Jul, 2020 - Comments: 1

This year’s IEEE Symposia on VLSI Technology and Circuits (VLSI 2020) included a presentation by NTT Docomo that looked far into the future of cellular communications, setting the stage for a broad industry shift in communication. This is far from trivial. 5G only just recently entered the commercial world, and — especially with the higher millimeter-wave (mmWave) frequencies — it has ... » read more

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