tag: imec

Manufacturing Bits: July 10
By Mark LaPedus - 10 Jul, 2018 - Comments: 0

Ruthenium interconnects Imec has developed a process to enable ruthenium (Ru) interconnects in chips at 5nm and beyond. Ru is one of several candidates to replace traditional copper as the interconnect material in chips. The interconnects, which reside on the top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another. The int... » read more

Where Is Selective Deposition?
By Mark LaPedus - 25 Jun, 2018 - Comments: 4

For years, the industry has been working on an advanced technology called area-selective deposition for chip production at 5nm and beyond. Area-selective deposition, an advanced self-aligned patterning technique, is still in R&D amid a slew of challenges with the technology. But the more advanced forms of technology are beginning to make some progress, possibly inching closer from the la... » read more

What’s Next In R&D?
By Mark LaPedus - 21 Jun, 2018 - Comments: 1

Luc Van den hove, president and chief executive of Imec, sat down with Semiconductor Engineering to discuss R&D challenges and what’s next in the arena. The Belgium R&D organization is working on AI, DNA storage, EUV, semiconductors and other technologies. What follows are excerpts of that conversation. SE: Moore’s Law is slowing down. And it is becoming more expensive to move fr... » read more

Dealing With Resistance In Chips
By Mark LaPedus - 21 Jun, 2018 - Comments: 2

Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

Big Trouble At 3nm
By Mark LaPedus - 21 Jun, 2018 - Comments: 0

As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm. Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-p... » read more

Blog Review: June 13
By Jesse Allen - 13 Jun, 2018 - Comments: 0

Synopsys' Taylor Armerding looks at what the flaws in OpenPGP and S/MIME encryption means for the IoT and warns that the problems of patching such devices could lead to an increasing chance of security failures. Cadence's Paul McLellan takes a peek at Imec's roadmap to see what the path to 3nm looks like, how nanosheets fit in, and why design and system technology co-optimization is necessar... » read more

New Transistor Types Vs. Packaging
By Ed Sperling - 11 Jun, 2018 - Comments: 0

Plans are being formulated for the rollout of multiple types of gate-all-around FETs and literally dozens of advanced packaging options. The question now is which ones will achieve critical mass, because there aren't enough chips in the world to support all of them profitably. FinFETs, which were first introduced by Intel at 22nm, are running out of steam. While they will survive 10/7nm, and... » read more

Extending The IC Roadmap
By Mark LaPedus - 11 Jun, 2018 - Comments: 0

An Steegen, executive vice president of semiconductor technology and systems at Imec, sat down with Semiconductor Engineering to discuss IC scaling and chip packaging. Imec is working on next-generation transistors, but it is also developing several new technologies for IC packaging, such as a proprietary silicon bridge, a cooling technology and packaging modules. What follows are excerpts of t... » read more

The Week In Review: Manufacturing
By Ed Sperling - 01 Jun, 2018 - Comments: 0

Cleanliness is a good thing. In the fab, it's also a very profitable thing. According to a report from Research and Markets, the wafer cleaning systems market will grow more than 6%. The research house notes, however, that the rate of growth is slowing. GlobalFoundries began volume production of its 180nm ultra-high-voltage process for industrial and power applications. The base platform sta... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 25 May, 2018 - Comments: 0

Chipmakers GlobalFoundries has announced that its 22nm FD-SOI technology platform has been certified to AEC-Q100 Grade 2 for production. As a part of the AEC-Q100 certification, devices must withstand reliability stress tests for an extended period of time and over a wide temperature range in order to achieve Grade 2 certification. Presto Engineering has joined GlobalFoundries’ ecosystem ... » read more

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