tag: imec

Inside Intel’s Ambitious Roadmap
By Mark LaPedus and Ed Sperling - 23 Aug, 2021 - Comments: 2

Ann Kelleher, senior vice president and general manager of Technology Development at Intel, sat down with Semiconductor Engineering to talk about the company’s new logic roadmap, as well as lithography, packaging, and process technology. What follows are excerpts of that discussion. SE: Intel recently disclosed its new logic roadmap. Beyond Intel 3, the company is working on Intel 20A. Wit... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 20 Aug, 2021 - Comments: 0

Chipmakers, OEMs At Intel’s Architecture Day this week, the company revealed several new chip architectures. Some were already announced, while others are new. These include Intel’s first performance hybrid architecture, a data center architecture, a discrete gaming graphics processing unit (GPU) architecture, infrastructure processing units (IPUs), and a data center GPU architecture. Here... » read more

Week In Review: Design, Low Power
By Jesse Allen - 20 Aug, 2021 - Comments: 0

Tools Cadence teamed up with Tower Semiconductor to release a silicon-validated SP4T RF SOI switch reference design flow using the Cadence Virtuoso Design Platform and RF Solution. The reference design flow targets advanced 5G wireless, wireline infrastructure, and automotive IC product development and include a set of mixed-signal and RF design, simulation, system analysis and signoff tools t... » read more

Angstrom-Level Measurements With AFMs
By Mark LaPedus - 19 Aug, 2021 - Comments: 0

Competition is heating up in the atomic force microscopy (AFM) market, where several vendors are shipping new AFM systems that address various metrology challenges in packaging, semiconductors and other fields. AFM, a small but growing field that has been under the radar, involves a standalone system that provides surface measurements on structures down to the angstrom level. (1 angstrom = 0... » read more

Stacked Nanosheets And Forksheet FETs
By Katherine Derbyshire - 19 Aug, 2021 - Comments: 0

What comes next after gate-all-around FETs is still being worked out, but it likely will involve some version of stacked nanosheets. The design of advanced transistors is a tradeoff. On one hand, it takes less gate capacitance to control a thin channel. On the other hand, thin channels can’t carry as much drive current. Stacked nanosheet designs seek to reconcile these two objectives by... » read more

Automotive Lidar Technologies Battle It Out
By Bryon Moyer - 05 Aug, 2021 - Comments: 1

Lidar is likely to be added to the list of sensors that future cars will use to help with navigation and safety, but most likely it won't be the large rotating mirror assembly on the top of vehicles. Newer solid-state radar technologies are being researched and developed, although it’s not yet clear which of these will win. “The benefits of lidar technology are well known dating back to ... » read more

The Great Quantum Computing Race
By Mark LaPedus - 26 Jul, 2021 - Comments: 0

Quantum computing is heating up, as a growing number of entities race to benchmark, stabilize, and ultimately commercialize this technology. As of July 2021, a group from China appears to have taken the lead in terms of raw performance, but Google, IBM, Intel and other quantum computer developers aren’t far behind. All of that could change overnight, though. At this point, it's too early t... » read more

Underlayer Optimization Method For EUV Lithography
By Brewer Science - 21 Jul, 2021 - Comments: 0

Photoresist and underlayer combine to serve a central role in EUVL for patterning. Layers will be very thin in future, because high numerical aperture (NA) and tight pitches will require very thin layers in the lithography stack. This thinness will make chemical interactions at the photoresist-underlayer interface more common. Adhesion between these layers will be critical to overcome pattern c... » read more

Manufacturing Bits: July 20
By Mark LaPedus - 20 Jul, 2021 - Comments: 0

Interference EUV lithography ESOL has developed a standalone interference extreme ultraviolet (EUV) lithography tool for use in R&D applications. The system, called EMiLE (EUV Micro-interference Lithography Equipment), is primary used to speed up the development of EUV photoresists and related wafer processes. The system is different than ASML’s EUV lithography scanners, which are ... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 09 Jul, 2021 - Comments: 0

Chipmakers and OEMs China has been working on compound semiconductors, such as gallium-nitride (GaN) and silicon carbide (SiC). Now, a China-backed company has taken a big step in the SiC and related markets. Chip supplier Nexperia, a subsidiary of China’s Wingtech Technology, has acquired Newport Wafer Fab (NWF), a U.K.-based manufacture of power and compound semiconductors, including Si... » read more

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