tag: Lam Research

Some Chipmakers Sidestep Scaling, Others Hedge
By Ed Sperling - 15 Nov, 2018 - Comments: 0

The rising cost of developing chips at 7nm coupled with the reduced benefits of scaling have pried open the floodgates for a variety of options involving new materials, architectures and packaging that either were ignored or not fully developed in the past. Some of these approaches are closely tied to new markets, such as assisted and autonomous vehicles, robotics and 5G. Others involve new ... » read more

EUV Mask Blank Battle Brewing
By Mark LaPedus - 15 Nov, 2018 - Comments: 2

Amid the ramp of extreme ultraviolet (EUV) lithography in the market, suppliers of EUV mask blanks are expanding their production. And a new player—Applied Materials—is looking to enter the market. AGC and Hoya, the two main suppliers of EUV mask blanks, are adding capacity for these critical components that are used for EUV photomasks. A mask blank serves as the substrate for a photomas... » read more

Blog Review: Oct. 31
By Jesse Allen - 31 Oct, 2018 - Comments: 0

Mentor's Joe Hupcey III digs into handling memories effectively with formal through abstraction and the easiest ways to address memory-related inconclusive results. Cadence's Paul McLellan explains DARPA's CHIPS program that aims to lower semiconductor design costs through chiplet-based designs, the current status of the work, and what the next steps will be. Synopsys' Sangeeta Kulkarni c... » read more

CMOS Area Scaling And The Need For High Aspect Ratio Vias
By Coventor - 26 Oct, 2018 - Comments: 0

Resolving internal routing congestion will be essential to enable CMOS area scaling to the N5 node and beyond. The solution will require new design maneuvers in place and route (PnR), as well as patterning innovations. In this work, we present inter-layer high aspect ratio vias or ‘SuperVia’ (SV) as one technology element that could enable track height scaling to 4.5T at aggressive N5 dime... » read more

3D NAND: Challenges Beyond 96-Layer Memory Arrays
By Steve Shih-Wei Wang - 24 Oct, 2018 - Comments: 0

Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the first V-NAND product using 24 layers and MLC [1]. Five years later, in 2018, vendors of 3D-NAND have all announced production plans for 96-Layer NAND using TLC [2]. According to recent news reports, vendors are already working ... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 19 Oct, 2018 - Comments: 0

Chipmakers Amid ongoing delays with its 10nm process, Intel has reorganized its manufacturing unit, according to a report from The Oregonian/OregonLive. Sohail Ahmed, who has jointly led the unit since 2016, will retire next month, according to the report. The industry is racing to put extreme ultraviolet (EUV) lithography into production. TSMC recently taped-out its first 7nm chip using E... » read more

EUV Pellicle, Uptime And Resist Issues Continue
By Mark LaPedus - 26 Sep, 2018 - Comments: 0

Extreme ultraviolet (EUV) lithography is moving closer to realization, but several problems involving scanner uptime, photoresists and pellicles need to be resolved before this long-overdue technology is put into full production. Intel, Samsung and TSMC are hoping to insert EUV into production at 7nm and/or 5nm. While the remaining issues don’t necessarily pre-empt using EUV, they do affec... » read more

Atomic Layer Etching: Rethinking the Art of Etch
By Lam Research - 20 Sep, 2018 - Comments: 0

Atomic layer etching (ALE) is the most advanced etching technique in production today. In this Perspective, we describe ALE in comparison to long-standing conventional etching techniques, relating it to the underlying principles behind the ancient art of etching. Once considered too slow, we show how leveraging plasma has made ALE a thousand times faster than earlier approaches. While Si is the... » read more

Cryogenic Etch Re-Emerges
By Mark LaPedus - 20 Sep, 2018 - Comments: 0

After years in R&D, a technology called cryogenic etch is re-emerging as a possible option for production as the industry faces new challenges in memory and logic. Cryogenic etch removes materials in devices with high aspect ratios at cold temperatures, although it has always been a challenging process. Cryogenic etch is difficult to control and it requires specialized cryogenic gases in... » read more

SiC Chip Demand Surges
By Mark LaPedus - 20 Sep, 2018 - Comments: 0

The silicon carbide (SiC) power semiconductor market is experiencing a sudden surge in demand amid growth for electric vehicles and other systems. But the demand also is causing a tight supply of SiC-based devices in the market, prompting some vendors to add fab capacity in the midst of a tricky wafer-size transition. Some SiC device makers are transitioning from 4- to 6-inch wafers in the f... » read more

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