Reflections On 2017: Manufacturing And Markets

By Brian Bailey - 28 Dec, 2017 - Comments: 0

People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. To see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but many have this year. This is the first of two parts that looks at the pred... » read more

Unsolved Litho Issues At 7nm

By Ed Sperling - 21 Sep, 2017 - Comments: 1

By Ed Sperling & Mark LaPedus EUV lithography is creating a new set of challenges on the photomask side for which there currently are no simple solutions. While lithography is viewed as a single technology, [gettech id="31045" comment="EUV"] actually is a collection of technologies. Not all of those technologies have advanced equally and simultaneously, however. For example, aberrations... » read more

Tech Talk: 7nm Litho

By Ed Sperling - 20 Jul, 2017 - Comments: 2

David Fried, chief technology officer at Coventor, digs into future scaling issues involving multi-patterning and new transistor types. https://youtu.be/FBnYRAL1xKY Related Stories Inside Next-Gen Transistors Coventor’s CTO looks at new types of transistors, the expanding number of challenges at future process nodes & the state of semiconductor development in China. Faster Time T... » read more

Photoresist Shape In 3D

By Mustafa Akbulut - 20 Apr, 2017 - Comments: 0

Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. Now, what you have on the mask determines only a part of what you will get at the end. You will only obtain your final product... » read more

Understanding How Small Variations In Photoresist Shape Significantly Impact Multi-Patterning Yield

By Coventor - 20 Apr, 2017 - Comments: 0

Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have been used to successfully increase semiconductor device density, circumventing prior physical limits in pattern density. However, the number of processing steps needed in these patterning schemes can make it difficult to directly translate a lithographic mask pattern to a fin... » read more

Inside Lithography And Masks

By Mark LaPedus - 05 Apr, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cove... » read more

Big Changes In Patterning

By Ed Sperling - 22 Feb, 2017 - Comments: 0

Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], sat down with Semiconductor Engineering to discuss patterning issues at 10nm and below, including mask alignment, the need for GPU acceleration, EUV's future impact on the total number of masks, and what the re-introduction of curvilinear shapes will mean for design. SE: Patterning issues are getting a lot of attention at 10nm and 7n... » read more

Battling Fab Cycle Times

By Mark LaPedus - 16 Feb, 2017 - Comments: 9

The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

FinFET And Multi-Patterning Aware Place-And-Route Implementation

By Mentor, a Siemens Business - 18 Jan, 2017 - Comments: 0

The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Nitro-SoC place and route system handles them. To read more, click here. » read more

Morphing Moore’s Law

By Ed Sperling - 15 Dec, 2016 - Comments: 0

In 1965, Gordon Moore defined a timetable for doubling the number of transistors on a piece of silicon every two years. The law, as he originally defined it, is now hopelessly outdated. Any attempts to apply it to the most advanced chips today are a stretch at best, and complete fiction at worst. No one is on a two-year cadence between process nodes anymore—not even Intel. In fact, no one ... » read more

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tag: multi patterning