tag: SiGe

Buried Si/SiGe Interfaces Investigated Using Soft X-Ray Reflectometry and STEM-EDX
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "Interface sharpness in stacked thin film structures: a comparison of soft X-ray reflectometry and transmission electron microscopy" was published by researchers at Physikalisch-Technische Bundesanstalt (PTB), imec, and Thermo Fisher Scientific Inc. The paper states: "A key element of semiconductor fabrication is the precise deposition of thin films. Among other... » read more

3D Metrology Meets Its Match In 3D Chips And Packages
By Laura Peters - 11 Jun, 2024 - Comments: 0

The pace of innovation in 3D device structures and packages is accelerating rapidly, driving the need for precise measurement and control of feature height to ensure these devices are reliable and perform as expected throughout their lifetimes. Expansion along the z axis is already well underway. One need look no further than the staircase-like 3D NAND stacks that rise like skyscrapers to p... » read more

Epi SiGe Application Using METRION In-Line SIMS System
By Nova - 07 Mar, 2023 - Comments: 0

The epitaxial process is a well-established deposition technique in semiconductor fabrication because it enables the ability to achieve much higher doping concentrations than can be obtained via ion implantation. As we move toward <5nm technology, a key process for enabling gate-all-around FET (GAAFET) is the stacked multi-lattice of Silicon (Si) and Silicon-germanium (SiGe) epi process for ... » read more

What’s Different About Next-Gen Transistors
By Katherine Derbyshire - 20 Oct, 2022 - Comments: 0

After nearly a decade and five major nodes, along with a slew of half-nodes, the semiconductor manufacturing industry will begin transitioning from finFETs to gate-all-around stacked nanosheet transistor architectures at the 3nm technology node. Relative to finFETs, nanosheet transistors deliver more drive current by increasing channel widths in the same circuit footprint. The gate-all-aroun... » read more

Synchrotron S-ray Diffraction-based Non-destructive Nanoscale Mapping of Si/SiGe Nanosheets for GAA structures
By Technical Paper Link - 13 Jun, 2022 - Comments: 0

New research paper titled "Mapping of the mechanical response in Si/SiGe nanosheet device geometries" from researchers at IBM T.J. Watson Research Center and Brookhaven National Laboratory. Sponsored by U.S. DOE. Abstract "The performance of next-generation, nanoelectronic devices relies on a precise understanding of strain within the constituent materials. However, the increased flexibilit... » read more

Highly Selective Etch Rolls Out For Next-Gen Chips
By Mark LaPedus - 21 Mar, 2022 - Comments: 0

Several etch vendors are starting to ship next-generation selective etch tools, paving the way for new memory and logic devices. Applied Materials was the first vendor to ship a next-gen selective etch system, sometimes called highly-selective etch, in 2016. Now, Lam Research, TEL, and others are shipping tools with highly-selective etch capabilities, in preparation for futuristic devices su... » read more

Transistors Reach Tipping Point At 3nm
By Mark LaPedus - 23 Feb, 2022 - Comments: 1

The semiconductor industry is making its first major change in a new transistor type in more than a decade, moving toward a next-generation structure called gate-all-around (GAA) FETs. Although GAA transistors have yet to ship, many industry experts are wondering how long this technology will deliver — and what new architecture will take over from there. Barring major delays, today’s GAA... » read more

What’s Next For Transistors And Chiplets
By Mark LaPedus - 21 Oct, 2021 - Comments: 5

Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Inspecting, Testing, And Measuring SiC
By Patrick Waurzyniak - 12 Oct, 2021 - Comments: 0

Achieving the auto industry's stringent zero defect goals is becoming a big challenge for makers of silicon carbide substrates, which are struggling to achieve sufficient yields and reliability as they migrate from 150mm to 200mm wafers and shift their focus away from pure silicon. SiC is a combination of silicon and harder carbide materials, and it has emerged as a key technology for batter... » read more

Behind The Intel-GlobalFoundries Rumor
By Ed Sperling - 19 Jul, 2021 - Comments: 5

A Wall Street Journal report that Intel is looking to buy GlobalFoundries has sparked discussions across the industry. But what exactly this would mean, and why now versus a couple years ago, needs some context. There are layers upon layers of irony behind this would-be deal, and it dates back decades to some rather famous encounters. Consider former AMD CEO Jerry Sanders' 1991 comment that ... » read more

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