Time To Revisit 2.5D And 3D

Chipmakers are reaching various and challenging inflection points. In logic, many IC makers face a daunting transition from planar transistors at 20nm to finFETs at 14nm. And on another front, the industry is nearing the memory bandwidth wall.

So perhaps it’s time to look at new alternatives. In fact, chipmakers are taking a hard look, or re-examining, one alternative—stacked 2.5D/3D chips. For years, the industry has been talking about the development of 2.5D and 3D chips using through-silicon vias (TSVs), whether those TSVs run through a die or a separate interposer die in 2.5D designs.

So far, though, 2.5D/3D technology is taking longer than expected to develop and only a smattering of chipmakers have shipped products in the market. As before, there are several challenges with the technology, such as design complexities, logistics, thermal issues and others. “The need is still there for 2.5D/3D and that has not changed,” said Jan Vardaman, president of TechSearch International, a market research firm. “There is progress in 3D ICs, but there are still yield and cost issues.”

Cost, considered one of the top challenges, comes in various forms. The high cost of the 2.5D/3D chips themselves have relegated stacked die to high-end, niche applications. Generally, 2.5D/3D chips are too expensive for the high-volume, price-sensitive mobile markets, at least for now.

Another reason for the high cost is fairly apparent—manufacturing issues. In fact, 3D TSV technology adds 15% or more in terms of total wafer processing costs, compared to a traditional planar flow, according to a study by North Carolina State University. And interposers add 25% or more to the cost of silicon before packaging, according to the study.

In response, the industry is taking steps to address some of the pieces in the manufacturing puzzle. Soon, the market will have new interposer suppliers, which could drive down the cost for these expensive components. In addition, the industry is looking for ways to reduce the cost in the 3D TSV production flow.

And as part of the manufacturing equation, chipmakers have plenty of foundry/OSAT vendors to choose from in the 2.5D/3D arena. The trick is to find the right partners. Each company offers a different business model. And each model has its advantages and disadvantages.

2.5D/3D drivers
Today, 3D technology is hot. The 3D NAND market is heating up, as Micron, Samsung and SK Hynix are making the transition from planar to 3D devices.

The stacked 2.5D/3D market is also taking root. The first wave of 2.5D/3D chips hit the market several years ago, when Toshiba and others shipped TSV-based CMOS image sensors. In the same wave, Xilinx shipped 2.5D-based FPGAs.

“You will begin to see the next wave of products soon,” said Rich Rice, senior vice president of business development at Advanced Semiconductor Engineering (ASE). “We are talking about 2.5D in 2014 and 3D in 2015. But even now, we are starting to see more and more 3D memory stacks in the market.”

For example, Micron is sampling its Hybrid Memory Cube (HMC). Tezzaron is also shipping 3D DRAMs. Soon, Hynix hopes to ship its own version of 3D DRAM technology, dubbed High Bandwidth Memory (HBM). And at some point, vendors will ship Wide-IO 2 technology.

3D DRAMs are critical for good reason. Clearly, there is a growing gap between memory bandwidth and overall system requirements, creating an unwanted I/O bottleneck. “We are talking about the memory wall,”said Sesh Ramaswami, managing director of TSV and advanced packaging product development at Applied Materials. “That’s where the problem is.”

The volume ramp for 3D DRAMs is expected in 2015, Ramaswami said. “Once that happens, that will take TSV to the next level,” he said. “Not all DRAMs will have TSVs. There might be a small subset (of 3D DRAMs in the market), where it brings value.”

Perhaps the next crop of 2.5D/3D chips will hit in 2015 or 2016. That group includes chips from Advanced Micro Devices, Nvidia and others. Still others believe the next group of chips may not necessarily come from the big names in the industry. “What we’ve seen is a huge pull from customers in military aerospace, medical and test equipment,” said Robert Patti, chief technology officer and vice president of design engineering at 3D memory supplier Tezzaron. “I would categorize these guys as early adopters. These chips are higher cost items, lower volumes and more specialized.”

Besides the memory wall, Patti said there is another driver for 2.5D/3D technology. “There is a compelling reason why some chip makers will need to move to advanced nodes,” Patti said. “But not many chipmakers are rapidly moving to 20nm or 14nm because of the cost impact of double patterning. If you look at the cost competiveness of 28nm versus 20nm and 14nm, 28nm will be the most cost-competitive process for at least the next three years. Quite frankly, unless EUV shows up in the near future, 28nm will be the cost-effective process for an even longer period. And so, if you want to look around at what I can do for the next year or two that can reduce my costs, the only technology that is waiting is really 2.5D/3D technologies.”

Finding the right partner
Chipmakers that wish to develop 2.5D/3D technology face several hurdles. Designing a product for the right market is one challenge. IC makers must also look for a suitable manufacturing partner, or partners, with a sound flow. “Whether its stacked DRAM or interposer, it will come down to who can handle the assembly process well, such that you have high yields,” Applied’s Ramaswami said.

Today, there are two schools of thought in 2.5D/3D manufacturing—turnkey versus a hybrid approach. TSMC and Samsung provide a turnkey solution, in which the companies provide both the front- and back-end work under the same roof. In contrast, GlobalFoundries, Novati and UMC provide a hybrid approach. In that model, the foundries handle the front-end steps, but pass on the back-end work to the IC packaging houses. Foundry startup Novati is a subsidiary of Tezzaron.

For now, there is room for both the turnkey and hybrid approaches. “I think both models will co-exist,” said David McCann, vice president of packaging R&D at GlobalFoundries.

There are also advantages and disadvantages in both approaches. In the hybrid approach, customers have the flexibility to work with various chip-assembly and component suppliers. The challenge is to integrate the pieces together and develop a part with good yields. And sometimes, it’s unclear who will take responsibility for any issues.

Meanwhile, in its turnkey approach, TSMC assumes control of the entire process, thereby ensuring the responsibility and quality of the final chip. TSMC’s process is also expensive. Surprisingly, one of the more expensive aspects of the flow is a simple part—the 65nm interposer.

In fact, TSMC and the other foundries are among the few suppliers of fine-pitch 2.5D interposers in the market, which, in turn, keeps the prices high for these components. “Generally, interposers go for about 25 cents per square millimeter. DRAM that you go buy at the local store goes for less than a nickel per square millimeter. So interposers, which have nothing but some wires on them, are selling for five times the cost of DRAMs,” said Tezzaron’s Patti. “But it isn’t going to stay that way. Ultimately, silicon interposers will get down to two cents per square millimeter.”

Interposer prices are expected to fall as more vendors enter the market, analysts said. Novati, for one, has begun ramping up silicon interposers. In a separate effort, ASE is teaming up with Inotera to co-develop silicon interposers. Over time, Inotera will provide cost-effective manufacturing services for interposers, said ASE’s Rice.

The other option is to procure organic interposers, which have some trade-offs. “I would expect organic is half the price of a silicon interposer,” Patti said. “But organic interposers do not provide as fine geometries as silicon.”

Go with 3D flow
Like 2.5D, the 3D TSV production flow is no bargain. Novati, for one, doesn’t consider itself the high-end 2.5D/3D foundry provider. Yet the starting price for a TSV flow at Novati goes for around $150,000. “That’s just to do the first engineering work. And then there is a repeating cost if you do more than the first lot of wafers. That is for a 1.2-micron diameter and 6-micron deep tungsten TSV,” Patti said.

3D TSV processing costs will increase as the devices themselves become more complex. “When you start stacking, you have quite a few modules in the process flow,” said An Steegen, senior vice president of Imec. “That adds cost.”

Imec’s 3D TSV process makes use of copper vias in an oxide clad as well as solder micro bumps for integration. A typical process can achieve a 10μm pitch with 5μm diameter TSVs in a 50μm thick wafer.

In Imec’s process, the front-side, via-middle TSV processing steps represent the most expensive part of the flow. Those steps, sometimes called the via creation process, represent some 42% of the cost in 3D TSV production, according to Imec. These steps include CMP, CVD, etch, lithography, plating and others. Of those, CMP is by far the most expensive step. “We are looking at whether you can avoid a CMP step,” Steegan said. “Can you even avoid slurry?”

Applied’s Ramaswami said that fab tool makers have addressed most, if not all, of the cost issues in the front-end flow. “The front-end costs have come down fairly dramatically,” he said. “If you look at the fab-type processes, the process flow in 2.5D/3D is 80% similar (to that of a traditional fab line). Once the flow is similar, and the equipment is available, then everyone knows how to reduce cost.”

Regarding CMP, the industry is still wrestling with the high-cost of the consumables, namely slurry. “When you look at CMP, it has an equipment part and consumables part. The equipment part is identical to equipment in any other CMP step. And, of course, there are parts that are a little bit different. You’re dealing with TSV-type barrier seed and copper. But in general, there are not many things we can do to reduce the cost,” Ramaswami said.

The real challenge, according to Ramaswami, resides in the backend or assembly steps in the 2.5D/3D flow. “What the industry needs to focus on is enabling an efficient, high yielding assembly process. If you look at assembly, I don’t believe you can have a slow ramp to yield because you are dealing with fully finished wafers,” he said.

In fact, many of the assembly steps are expensive. The front-side, via-middle TSV processing steps are the most expensive, followed by the copper pillar process (12%), wafer backside (12%), backside passivation (9%), wafer thinning (9%), wafer bonding to carrier (8%), wafer edge trimming (8%) and wafer debonding (1%), according to Imec.

As before, the temporary wafer bonding and debonding process remains a bottleneck due to the throughput of the systems. “Temporary bond/debond is still maturing,” Ramaswami said.

Most, if not all, of these manufacturing issues are getting resolved. But still, don’t expect an avalanche of products, at least in the near term. “We expect 2.5D/3D will be a gradual ramp, where the applications come into play at the right cost points,” he added.