Week In Review: Auto, Security, Pervasive Computing

Automotive
Synopsys added support for Infineon‘s automotive AI chip, the AURIX TC4xx 32-bit microcontroller with parallel processing unit.

Dialog Semiconductor announced automotive qualification for its DA7280 high-definition haptic driver. The company Alps Alpine is using the DA7280 in Alps Alpine Heavy, the latest version of its HAPTIC Reactor Linear Resonant Actuators (LRAs).

Bosch, Mercedes-Benz, and garage operator Apcoa are testing automated driverless valet parking at Stuttgart airport. Yellowstone, the U.S. national park, is experimenting with autonomous tourist shuttles, run by Beep. (Just don’t let the bear on the bus.)

Qualcomm participated in China’s recent 2020 C-V2X Cross-industry & Large-scale Pilot Plugfest — a live test and demonstration of cellular vehicle-to-everything (C-V2X) — with 100 other companies. The test included 40 automakers, 40+ terminal manufacturers, 10+ chipset solution vendors, 20+ information security vendors, 5 map providers, and 5 position vendors, according to a press release.

Security
Arm marked the first anniversary of its Morello Program, a five-year research initiative to boost the security in digital computing, by releasing prototype architecture specifications. The architecture uses principles defined in the Capability Hardware Enhanced RISC Instructions: CHERI Instruction – Set Architecture, from the University of Cambridge and SRI International. Arm also released a platform model, an Open Source Software project and tool chains, and technical support via a reference manual and dedicated forum. The Morello Program, funded by the UK government’s Industrial Strategy Challenge Fund (ISCF) Digital Security by Design (DSbD) program, also has participation from Google, Microsoft, the University of Cambridge, and the University of Edinburgh. A Morello board is targeted to be available for Q1 2022.

Rambus announced availability of its high-performance IPsec Packet Engine for securing traffic over a 5G networks at data rates from 1 to 10 Gbps. The IPsec has integrated DPDK and companion key negotiation toolkit for securing 5G network traffic. It supports 3GPP, PDCP, TLS, SSL, DTLS, IPsec protocols, as well as a broad portfolio of NIST-compliant algorithms.

U.S. hospitals are being attacked by ransomware coming from Russian cyber criminals, Bloomberg reports. The U.S. government issued an advisory this week.

Pervasive computing — data centers, cloud, 5G, IoT, edge
Japan may try building data centers in colder areas to cool the data centers and help achieve zero emissions, according to Bloomberg.

Marvell and Inphi announced a definitive agreement in which Marvell will acquire Inphi and reorganize itself. The combined company will be headquartered in the United States, as a U.S. semiconductor $40 billion company. Inphi’s high-speed data interconnect platform will give Marvell better opportunity in cloud and 5G.

AMD plans to acquire FPGA company Xilinx for $35 billion. The deal will “capitalize on opportunities spanning some of the industry’s most important growth segments from the data center to gaming, PCs, communications, automotive, industrial, aerospace and defense,” according to AMD’s press release.

Flex Logix detailed PCIe-board versions of its InferX X1 AI accelerator chip, which is designed for edge, at the Linley Fall Processor Conference. The boards will be inexpensive but will pack a lot of AI punch. Flex Logix is seeing some models running on InferX X1 AI accelerator chip in their own lab outperforming the popular Nvidia Tesla T4 chip. The boards will sell for as low as $399 for a 533MHz for the X1P1 to $999 for an 800MHz for the X1P4 board. The InferX X1P1 board uses one InferX X1 chip and a single LPDDR4x DRAM on a half-height, half-length PCIe board. General sampling will occur in Q1 and production availability in Q2 2021. The InferX X1P4 board, running YOLO3, will be comparable to popular Nvidia Tesla T4 chip but will be more affordable at $649-$999. Flex Logix also unveiled a suite of software tools to use with the boards. In addition to external APIs to streamline configuring the boards, the InferX boards will have a compiler flow from TensorFlowLite/ONNX models and an nnMAX runtime application.

Xilinx introduced its Zynq RFSoC DFE, an adaptive radio platform with hardened digital front-end (DFE) blocks and adaptable logic to designed to meet the evolving standards of 5G NR wireless applications.

Intel is acquiring SigOpt, a San Francisco-based AI software company.

5G will account for more than half of total mobile connections in North America, according to the latest ‘Mobile Economy North America 2020’ report from GSMA Intelligence.

Military/aerospace
Ansys signed a definitive acquisition agreement to acquire the 30-year-old company Analytical Graphics, Inc. (AGI), which provides simulation, modeling, testing, and analysis software for aerospace, defense, telecommunication and intelligence applications. If it clears regulatory approval, the $700 million deal is expected to close in Q4 2020. Ansys wants to do mission-focused analysis, and cites simulating satellite constellations. “AGI’s software will help its customers design, launch, and safely operate the next generation of satellite constellations,” according to a press release.

The satellite PhiSat-1’s hyperspectral-thermal camera and onboard AI processing uses Intel Movidius Myriad 2 Vision Processing Unit (VPU).

Advanced nodes
Samsung Foundry has been busy. The foundry and Cadence continue to collaborate on design flows for advanced nodes, which will benefit automotive, data center, AI, and mobile markets, among others. This week they announced custom and analog/mixed-signal (AMS) IC design flow for Samsung Foundry’s 3nm gate-all-around (GAA) process. Cadence’s certified flow includes its Virtuoso product and various other products. The flow is used for schematic migration, circuit design and verification, analog layout, physical verification and signoff, and custom digital and P&R digital layout.

Similarly Samsung Foundry and Synopsys released a AMS Design Reference Flow for Samsung Foundry’s 3nm GAA process, using the Synopsys Custom Design Platform. It has been optimized for designers of advanced 5G, high-performance compute (HPC), AI, and IoT applications.

Samsung Foundry has also been working with Synopsys on certified digital implementation, timing, and physical signoff reference flow for HPC designs using the Synopsys Fusion Design Platform. Synopsys and Samsung Foundry also collaborated on a portfolio of optimized interoperable process design kits (iPDKs) and methodologies for advanced custom design.

Ansys certified its multiphysics suite of semiconductor design tools on Samsung Foundry’s FinFET process technologies (14nm, 11nm, 10nm, 8nm, 7nm, 5nm, and 4nm).

Video of the week

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