Week In Review: Design, Low Power

Infineon buys precision electroplating firm; AI chip design; new RISC-V extensions; new Arm servers.


Infineon Technologies acquired Syntronixs Asia, which specializes in precision electroplating, a key process in the assembly process of semiconductors. Syntronixs Asia has a workforce of more than 500 people and has been a major service provider for Infineon since 2009. “Through this acquisition, we have made another important step to strengthen the resilience of our supply chain,” said Thomas Kaufmann, Executive Vice President and COO of Infineon’s Automotive Division. Based in Melaka, Malaysia, Syntronixs Asia was founded in 2006. Terms of the deal were not disclosed.

Alphawave IP will acquire Precise-ITC, a provider of Ethernet and Optical Transport Network (OTN) communications controller IP, for $25 million in cash based on achievement of certain performance milestones, plus customary stock-based retention incentives for the Precise-ITC team. The combined Alphawave IP and Precise-ITC IP solutions have already been integrated and fabricated in silicon products for several of Alphawave IP’s Product IP customers. The acquisition is Alphawave IP’s first such transaction since the completion of its IPO in May 2021. It is expected to close in January 2022.

A subsidiary of patent acquisition and licensing company WiLAN acquired a patent portfolio from an unnamed “publicly-traded leader in semiconductor technologies.” The acquired patents relate to wired connectivity functionality, including various USB-C technologies used in a wide range of applications such as desktop and laptop computers, tablets, mobile phones, gaming consoles, and smart TVs.

The U.S. Federal Trade Commission is the latest government agency to put up barriers to Nvidia’s $40 billion acquisition of Arm. The FTC sued to stop the deal, arguing that the combined firm could harm competition in several markets, particularly high-level ADAS, DPU SmartNICs, and Arm-based CPUs for cloud and data center. It also is concerned the deal would give Nvidia access to the competitively sensitive information of Arm’s licensees. “The FTC is suing to block the largest semiconductor chip merger in history to prevent a chip conglomerate from stifling the innovation pipeline for next-generation technologies,” said FTC Bureau of Competition Director Holly Vedova. “Tomorrow’s technologies depend on preserving today’s competitive, cutting-edge chip markets. This proposed deal would distort Arm’s incentives in chip markets and allow the combined firm to unfairly undermine Nvidia’s rivals.” Nvidia says that Arm’s IP licensing business will remain neutral.

Samsung Electronics used Synopsys’ DSO.ai AI-based design system along with Fusion Compiler RTL-to-GDSII solution to successfully complete a state-of-the-art, high-performance design at an advanced process technology. “Not only have we demonstrated that AI can help us achieve PPA targets for even the most demanding process technologies, but through our partnership we have established an ultra-high-productivity design system that is consistently delivering impressive results,” said Thomas Cho, EVP of Infrastructure & Design Technology Center, System LSI Business, Samsung Electronics.

Synopsys reported fourth quarter and full year financial results for 2021. For the quarter, revenue was $1.152 billion, up 12.4% from $1.025 billion in Q4 2020. For the 2021 fiscal year, revenue was $4.204 billion, an increase of 14.1% from $3.685 billion in FY 2020. “In addition to fiscal year 2022 expectations of strong double-digit revenue growth, continued operating margin expansion, EPS growth in the mid-teens range, and nearly $1.5 billion in operating cash flow, we are also raising our long-term financial objectives, with increased EDA and IP revenue growth expectations,” said Aart de Geus, chairman and co-CEO of Synopsys.

SPEC Innovations applied Ansys’ simulation solutions to develop a digital twin of a lunar rover to better enable Moon excavation in response to NASA’s Break the Ice Lunar Challenge. SPEC Innovations integrated its cloud-based web application Innoslate with Ansys SpaceClaim 3D modeling software and AGI Systems Tool Kit analysis platform to validate mission processes during design analysis and reduce time and cost.

Axiomise expanded its formal verification training program, now offering courses for beginners through experts. The courses are tailored to training students depending on their experience and skill in formal verification theory and emphasizes an industrial application methodology.

LeapMind launched the second version of its ultra-low power AI inference accelerator IP Efficiera. Specialized for convolutional neural network (CNN) inference processing, it runs as a circuit on FPGA or ASIC devices. The company says that by minimizing the number of quantization bits to 1 – 2 bits, it maximizes the power and area efficiency of convolution that accounts for most of inference processing without the need for advanced semiconductor manufacturing processes or special cell libraries.

Arasan Chip Systems uncorked MIPI I3C PHY I/O IP, in compliance with MIPI I3C v1.1. Part of Arasan’s Total IPTM Solution for MIPI I3C v1.1, The 2-wire MIPI I3C PHY I/O consolidates the features of I2C and SPI leading to an overall low pin count, shorter signal path, simplified design, and reduced power and cost. It operates in sync with the IP core’s clock rates up to 12.5 MHz and provides options for higher performance and high data rates.

RISC-V International ratified 15 new specifications representing more than 40 extensions to the open RISC-V ISA. Notable ratifications include the Vector, Scalar Cryptography, and Hypervisor specifications. The Vector specification aims to accelerate the computation of data intensive operations like ML inference for audio, vision, and voice processing. The Hypervisor specification virtualizes supervisor-level architecture to efficiently host guest operating systems atop a type-1 or type-2 hypervisor for cloud and embedded applications. The Scalar Cryptography specification enables the acceleration of cryptographic workloads for small footprint deployments such as IoT and embedded devices.

Codasip adopted Imperas reference designs and the Imperas DV solution for its RISC-V processor IP. Codasip said it included Imperas reference models in its DV testbenches to ensure an efficient verification flow that accommodates a range of flexible features and options while scaling across the entire roadmap of future cores.

The latest version of IAR Systems’ IAR Embedded Workbench for RISC-V, version 2.11, now supports the energy-efficient low-power L30 and L50 embedded processors from Codasip. Embedded Workbench is a C/C++ compiler and debugger toolchain in one IDE.

MIPS extended its use of Imperas’ simulation and verification tools as it transitions to RISC-V. Since 2010, the MIPS core IP deliverables have included the Imperas based instruction set simulator (ISS). “RISC-V is at the forefront of a hardware design renaissance in optimized processors,” said Itai Yarom, VP of sales and marketing at MIPS. “But, an ISA only provides the envelope of possibilities. The art and science of processor optimization requires complete feature exploration and verification, which are supported by the reference model simulation and verification technology from Imperas.”

SiFive revealed its Performance P650 processor. Based on RISC-V, it targets performance-demanding application processor markets and provides a 40% performance increase per clock cycle and overall 50% performance gain compared to its predecessor. It is scalable to sixteen cores using a coherent multicore complex and includes essential system components such as platform-level memory management and interrupt control units. It supports the new RISC-V hypervisor extension for virtualization.

Andes Technology updated its superscalar multicore AndesCore 45MP family and its AndesCore NX27V commercial RISC-V vector processor IP. Compared to the previous versions, the 8-stage superscalar multiprocessor A(X)45MP has 3x memory bandwidth while raising the floating-point performance by over 20% as measured by Whetstone benchmark. The NX27V is upgraded with full configurations of 128-bit to 512-bit VLEN/SIMD/MEM. For vector data types, the NX27V now implements FP16 to FP64 and Int8 to Int64 as well as Andes-enhanced BF16 and Int4 for optimized AI data representations.

Microchip Technology announced the Smart Embedded Vision development platform for designers using its PolarFire RISC-V SoC FPGA. The platform aims to simplify edge-compute solution development in the thermally challenging environments of the industrial IoT and factory automation applications.

AWS and Arm announced AWS Graviton3, the latest generation of the Arm-based server processors, as well as C7g instances powered by them. The companies said Graviton3 delivers 25% more performance for compute intensive workloads, up to 2x floating point performance on machine learning, gaming, and media encoding workloads, and up to 2x faster performance for cryptographic workloads, while using up to 60% less energy. Graviton3 also supports bfloat16 data for better performance for machine learning workloads.

Cadence, TSMC, and Microsoft collaborated on utilizing a cloud infrastructure to accelerate digital timing signoff of 10+ billion transistor designs. The group produced a white paper containing cloud scaling strategies focused on distributed execution, detailed illustrations of the Cadence Tempus Timing Signoff Solution cloud execution, sample scripts, Cadence CloudBurst reference architecture and Microsoft’s Azure Cloud IT best practices. “Over the past year, our close collaboration with Cadence and Microsoft through the TSMC OIP Cloud Alliance has given our mutual customers access to our advanced technologies, Cadence signoff solutions and cloud portfolio as well as Microsoft’s Azure platform to seamlessly handle giga-scale designs and quickly launch their differentiated products to market,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC.

Siemens Digital Industries Software and AWS inked a strategic collaboration agreement to expand cloud capabilities in Siemens‘ Xcelerator as a Service portfolio and accelerate adoption of new digital twin solutions using AWS IoT TwinMaker, which is compatible with Siemens’ software. The companies will also work together on customer support and new solutions.

Fraunhofer IIS’ mioty protocol stack for LPWAN and IoT applications was implemented and tested in Silicon Labs’ wireless bidirectional sub-GHZ SoC Series 2 platform EFR32FG23 (FG23). “The combination of mioty and our wireless hardware will enable high-performance and secure connectivity for IoT devices. The very compelling test results by Fraunhofer IIS verifies how our FG23 platform enables IoT end nodes to achieve 1+ mile wireless range while operating on a coin cell battery for 10+ years,” said Ross Sabolcik, VP/GM of Industrial & Commercial IoT Products, Silicon Labs. “Low-power, long range, and security are fundamental requirements in the rapidly expanding IoT deployments of Industrial IoT, Smart Cities, and Smart Buildings.”

Macronix brought its 1.2V Serial NOR Flash memory to market with its ultra-low-power, high-speed 120MHz MX25S line of Serial NOR Flash. The company said its power consumption is 50% of 1.8V Serial NOR Flash memories. It targets IoT, wireless communications, and consumer applications.

Quantum computing
Finland’s first quantum computer is up and running. The 5-qubit machine was created by VTT Technical Research Centre of Finland alongside quantum hardware startup IQM. It is located at Micronova, part of OtaNano, the national research infrastructure for micro and nanotechnology, jointly run by VTT and Aalto University. “This is just the first phase of the delivery and because of our ability to upgrade the systems, we are looking forward to working with VTT on delivering the 20-qubit and the 50-qubit systems,” said Jan Goetz, CEO and co-founder of IQM. The 50-qubit system is targeted for 2024.

The merger between Honeywell Quantum Solutions and Cambridge Quantum is complete. The new company is called Quantinuum. Its first product, which will remain platform agnostic, will focus on quantum cyber security, with an enterprise software package planned for 2022 that applies quantum computing to solve complex scientific problems in pharmaceuticals, materials science, specialty chemicals and agrochemicals. Honeywell will initially be the largest shareholder of Quantinuum with an approximately 54% ownership stake. Honeywell has also invested nearly $300 million in the new venture.

IDC predicts rapid growth for the quantum computing market, forecasting customer spend to grow from $412 million in 2020 to $8.6 billion in 2027, a 6-year compound annual growth rate (CAGR) of 50.9%. It also expects that investments (including public, private, internal R&D, and VC) in the quantum computing market will grow at a 6-year CAGR (2021-2027) of 11.3% and reach nearly $16.4 billion by the end of 2027.

Codasip appointed Ron Black as CEO. Black previously held the position of Executive Chairman for the company. Following his transition to CEO, the company will be hiring a non-executive Chairman. Codasip founder and former CEO Karel Masařík will become President and responsible for advanced research. The company announced several appointments recently, including Brett Cline as Chief Revenue Officer, Rupert Baines as Chief Marketing Officer, and Simon Bewick as Director of the UK Design Center.

Jochen Hanebeck will take over as the new CEO of Infineon Technologies in April 2022. The contract will last for five years. He has been a member of the Management Board and Chief Operations Officer since 2016 and with Infineon since 1994. He succeeds Reinhard Ploss, who has led the company as CEO since 2012. “Jochen Hanebeck has already contributed significantly to Infineon’s profitable growth trajectory over many years in various leadership positions. With him as CEO, the company will continue its success in the undoubtedly demanding times ahead,” said Wolfgang Eder, Chairman of the Supervisory Board of Infineon.

Trac Pham, CFO of Synopsys, intends to retire in 2022. To ensure an orderly transition, Pham will remain in his current role until a successor is in place. He has been CFO since 2014 and with Synopsys for 15 years.

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