Week In Review: Design, Low Power

Intellectual Property
Flex Logix inked an agreement with the Air Force Research Laboratory, Sensors Directorate (AFRL/RY) covering any Flex Logix IP technology for use in all US Government-funded programs for research and prototyping purposes with no license fees. “Our first license with AFRL for EFLX eFPGA in GlobalFoundries 12nm process was highly successful, with more than a half dozen projects licensing EFLX in the first year,” said Geoff Tate, CEO and Co-founder of Flex Logix. “Since many USG programs start with successive proof-of-concept chips before the programs are fully funded for production, it made sense to expand our agreement to include other process nodes. Those programs will now have access to Flex Logix products in foundry processes ranging from low-power 40nm to 7nm, including radiation hardened by design implementations and future supported processes such as 5nm.”

Vidatronic added 5nm finFET power management IPs for integration into SoCs for advanced microprocessor and high-speed serial interface applications. The series includes multiple low dropout (LDO) voltage regulator IPs, bandgap voltage reference IP, and integrated support blocks including power-on reset (POR), power-ok, and DAC.

OpenEdges Technology announced its 12nm LPDDR5/4/4x ORBIT PHY IP. The PHY uses an architecture with a highly configurable channel and floorplan to provide flexibility in connecting to different DRAM package types and lane ordering. It includes a proprietary programmable state machine (PSM) for accelerated firmware-based training and DFT functionality.

Arasan Chip Systems released ultra-low power standalone MIPI D-PHY Tx only IP and Rx only IP for the GlobalFoundries 12nm finFET node. Using the D-PHY IP as a standalone Tx and Rx saves area and power, especially in SoCs with multiple camera interfaces, making it suited for wearables and IoT display applications as well as automotive SoCs with multiple camera interfaces.

Photonics
GlobalFoundries introduced its silicon photonics platform, GF Fotonix, which combines 300mm photonics and 300GHz-class RF-CMOS features on a silicon wafer. Numerous companies announced support for the platform and process design kit (PDK).

Ansys and GF developed a process file with which customers can create custom components to consolidate complex processing onto a single chip for high-speed, low power consumption data transmission. The process file works in tandem with Ansys’ photonics simulation software, enabling designers to simulate 3D geometries with predictive accuracy, including correct layer thicknesses, material data and more, in accordance with GF’s design flow and process design kit specifications. GF will also leverage the Ansys Lumerical Photonic Verilog-A Platform, which provides the ability to combine custom components and foundry PDK components in the same circuit, both modelled using Verilog-A, and to run sophisticated bidirectional photonic circuit simulation.

Cadence’s integrated electronic/photonic design environment has been optimized for GF Fotonix, offering mutual customers a platform for electronic/photonic design, simulation, and analysis, and includes a robust set of features and APIs for generating and editing complex curvilinear shapes, waveguides and other photonics components.

Synopsys will support the PDK offered by GF with an end-to-end design flow that includes schematic capture and layout synthesis with OptoCompiler, simulation, and design rule checking (DRC) and layout versus schematic (LVS). The unified platform supports PDK-driven design and custom design with Synopsys’ Photonic Device Compiler.

Other companies announced they are, or will be, using the platform for upcoming products:

Ayar Labs has been in a strategic partnership with GF for several years to develop a photonics and electronics optimized platform that would support its monolithic in-package optical I/O chiplet and multi-wavelength optical source using high volume manufacturing, high volume process control, and existing CMOS materials. The two companies also developed an advanced electro-optic PDK that will be released in Q2 2022.

Ranovus released protocol-agnostic 100G optical I/O chiplets and IP cores based on GF Fotonix that can be integrated with processors, switches, and memory appliances to enable new data center architectures. The optical I/O can scale from 8- to 32-cores in the same footprint by combining Ranovus’ 100Gbps per wavelength monolithic EPIC (Electro-Photonic Integrated Circuit) cores with its proprietary laser and advanced packaging technologies.

Xanadu will use the GF Fotonix platform for high-volume manufacturing of photonic chips for implementing quantum error correction in universal and fault-tolerant quantum computers. Xanadu’s architecture implements error correction on silicon photonic chips that operate fully at room temperature, using photodetector technology borrowed from the optical telecommunications and lidar industries.

PsiQuantum will use the platform to develop custom silicon photonics chips.

Cisco Systems and GF are partnering on a custom silicon photonics solution for DCN and DCI applications, including an interdependent PDK.

Nvidia is working with GF to design high-bandwidth, low-power optical interconnects for some of its leading-edge data center products.

Lightmatter introduced a general-purpose photonic AI inference accelerator. Supporting a wide range of AI models, it offers up to 6.4 Tbps of optical interconnect for multi-blade scale-out, 1TB of DDR4 DRAM, and 3TB of solid-state memory in a 4-U server blade form factor. The company also announced a wafer-scale programmable photonic interconnect that integrates transistors and photonics, including lasers, modulators, and photodetectors.

Marvell introduced a cloud-optimized co-packaged optics (CPO) technology platform, to enable faster connectivity while reducing power consumption. The new platform includes 2.5D/3D highly integrated silicon photonics including lasers, TIAs, drivers, and PAM4 DSP.

Wireless
Keysight was granted a Federal Communications Commission (FCC) Spectrum Horizons Experimental license for developing 6G technology in sub-Terahertz (THz) frequency bands, between 95 gigahertz (GHz) and 3 THz. “Innovations in sub-THz spectrum will support use-cases such as immersive telepresence, digital twins and extended reality, which is all real-and-virtual combined environments and human-machine interactions generated by computer technology and wearables,” said Roger Nichols, Keysight’s 5G & 6G program director. “Using the FCC Spectrum Horizons license enables Keysight to strengthen our commitment to 6G technology, which will allow innovators to pioneer across the novel terrain of future-generation communications systems.”

Keysight also updated its 5G Network Emulation Solution to support the latest 3GPP Rel-15/16/17 features. Updates include extended frequency range coverage, flexible use of new wider bandwidth RF resources, processing power to support more carrier aggregation with >10CC, improved uplink capabilities to support features like uplink antenna switching and multi-Angle-of-Arrival testing, and multi-SIM support.

Chips
Analog Devices will invest €100 million (~$110 million) over the next three years in ADI Catalyst, a 100,000 square foot custom-built facility for innovation and collaboration located at its campus in the Raheen Business Park in Limerick, Ireland. It will primarily focus on the development of software-enabled solutions and AI technologies in areas such as Industry 4.0, sustainable energy, automotive electrification, and next generation connectivity.

Sleepiz used Infineon’s XENSIV 60 GHz radar technology in a sleep monitoring system that can be integrated into connected smart home device ranging from smart speakers to bed lamps. “Infineon’s XENSIV radar sensors offer a great opportunity for healthcare applications as they allow to accurately measure vital signs such as heartbeat and breathing rate without touching the body or intruding on privacy,” said Philipp von Schierstaedt, Senior Vice President and General Manager Radio Frequency & Sensors at Infineon.

Quantum computing & HPC
QuantWare launched a 25-qubit quantum processing unit (QPU) based on superconducting technology. The company says an ‘off-the-shelf’ quantum processor will enable companies to quickly build their own quantum systems. It includes the option to add chip features as desired, such as asymmetric squid junctions, Purcell filters, and custom qubit topology. Dedicated drive and flux lines offer full qubit control. “Building a large-scale, full-stack quantum computer can cost in the region of €45 million. The Contralto creates the opportunity to build one for an order of magnitude lower cost, opening up a myriad of new opportunities which could not be explored before,” said QuantWare managing director Matthijs Rijlaarsdam.

A group coordinated by Fraunhofer IAF is working to develop a compact, scalable quantum processor based on spin qubits in diamond that can be connected to classical computers. Funded with €16.1 million (~$17.5 million), the SPINNING project aims to develop hardware with longer operation times and smaller error rates as well as low cooling requirements compared to current quantum systems. The quantum processor will initially be able to compute with 10 qubits, subsequently expanding to 100 qubits and more, and would be able to predict the products of complex quantum chemical reactions. “One of the goals of our work is to ensure reliable operation of such an innovative quantum computer and to create a periphery to make the computing power available to a broad group of users, for example via cloud computing,” said Rüdiger Quay, project coordinator of SPINNING and executive director of Fraunhofer IAF. Others members of the group include Fraunhofer IISB, Forschungszentrum Jülich, Karlsruhe Institute of Technology, University of Konstanz, Heidelberg University, Technical University of Munich, Ulm University, Diamond Materials, NVision Imaging Technologies, Qinu, University of Stuttgart, Quantum Brilliance, Swabian Instruments, and 14 other partners from science and industry.

India’s National Supercomputing Mission deployed the PARAM Ganga petascale supercomputer at Indian Institute of Technology Roorkee. Substantial components utilized to build this system were manufactured and assembled within India along with a software stack developed by the Centre for Development of Advanced Computing (C-DAC).  The system has a peak capacity of 1.66 Petaflops and will serve a range of engineering and scientific research.

Storage
Kioxia uncorked its PM7 Series of enterprise 24G SAS SSDs. Using Kioxia’s 5th generation BiCS FLASH 3D TLC flash memory, the PM7 Series delivers sequential read performance of up 4.2 GB/s, 720K random read IOPS and up to 355K random write IOPS. They are available in capacities up to 30.72 TB. The series is FIPS2 140-2 certified and currently under test for FIPS 140-3 certification.

Automotive & safety
Intel is planning to take its Mobileye business public. Mobileye develops computer vision SoCs for automotive ADAS and autonomous driving. Intel acquired the company in 2017. The number of shares to be offered and the price range for the proposed offering have not yet been determined.

Renesas introduced an SoC for central processing in ADAS and automated driving (AD) solutions. Targeting L2+ and L3 applications, R-Car V4H reaches deep learning performance of up to 34 TOPS for high-speed image recognition and processing of surrounding objects by automotive cameras, radar, and lidar. It includes four Arm Cortex-A76 at 1.8 Ghz, three lockstep Cortex-R52 cores at 1.4 Ghz, ISP, and AXM-8-256 CPU at 600MHz.

Rambus’ Root of Trust RT-640 Embedded Hardware Security Module (HSM) received Automotive Safety Integrity Level B (ASIL-B) certification per the ISO 26262 standard from TÜV-SGS. RT-640 silicon IP design provides cryptographic functions, safety mechanisms, and anti-tamper technologies to protect critical automotive electronics and data. “Increasingly sophisticated automotive systems must be both functionally safe and resilient to cyberattack,” said Neeraj Paliwal, general manager of Security IP at Rambus. “With the Rambus RT-640 Embedded HSM, automotive manufacturers get the best of both worlds: robust cybersecurity anchored in hardware with the assurance of ASIL-B functional safety. We have already achieved multiple design wins for the RT-640 across the globe, and it has tremendous traction in the new centralized automotive architecture across ADAS and sensors such as cameras, lidar and radar.”

Renesas added functional safety solutions that meet the IEC61508 standard for both its RA and RX families of microcontrollers. It now offers IEC 61508 SIL3i certified self-test software for both Arm Cortex-M23 and -M33-based MCUs, as well as IEC 61508 SIL3 certified PROFIsafe Application Software for RX MCUs. “The diagnostic software added to the Renesas solution, issued by TÜV Rheinland for functional safety certification, is based on the Arm core, which is increasingly being adopted in industrial automation,” said Masataka Nakao, General Manager, responsible for Functional Safety in Business Stream Industrial Services and Cybersecurity at TÜV Rheinland Japan. “Verifying diagnostic software takes time, and we are confident that certified Renesas diagnostic software can increase the efficiency of customers’ functional safety product development, which will contribute to the expansion of the functional safety market.” Also available is reference documentation, an evaluation board for the RX family, and an IEC 61508 Certification Kit for RX compilers.

Space
QuickLogic debuted a “fast boot” rad-hard eFPGA IP available to users of SkyWater’s 90nm rad-hard (RH90) process. This technology can be embedded as an IP core in ASIC and SoC devices or implemented as a custom rad-hard FPGA for mission critical or ruggedized aerospace, defense, and commercial applications.

STMicroelectronics announced a series of radiation-hardened power, analog, and logic ICs in low-cost plastic packages targeted at small, low-cost satellites that deliver services like earth observation and broadband internet from low-earth orbits (LEOs). The first nine devices in this series include a data converter, a voltage regulator, an LVDS transceiver, a line driver, and five logic gates that are used throughout systems like power generation and distribution, on-board computers, telemetry star trackers, and transceivers.

Education
Codasip uncorked a university program that augments graduate and undergraduate computer engineering curriculums with materials and assignments and grants access to Codasip RISC-V custom development tools and CodAL high-level synthesis language. ” We are engaged with multiple universities in curriculum development and research activities, and look forward to welcoming additional universities into the Program,” said Keith Graham, the lead of Codasip’s University Program.

Read more news at Manufacturing, Test and Auto, Security, Pervasive Computing.