What’s Next For Memory?

Apple, Samsung and others are developing the next wave of smartphones and tablets. OEMs want to integrate new memory schemes that provide more bandwidth at lower power. But there are some challenges in the arena that are prompting memory makers to rethink their mobile DRAM roadmaps.

The conventional wisdom was that memory makers would ship mobile DRAMs based on the new LPDDR4 interface standard in 2014. Then, the mobile industry eventually would ditch planar-based mobile DRAMs and make a giant leap to Wide I/O-2, a 3D DRAM technology using through-silicon vias (TSVs).

Today, Micron, Samsung and SK Hynix are shipping LPDDR4-based mobile DRAMs, which are specialized, low-power versions of PC DRAM. But as part of the new and surprising changes in the roadmap, Micron and Samsung likely will extend planar-based mobile DRAMs and are developing an evolutionary scheme called LPDDR5.

For now, however, it’s doubtful that the industry will extend PC DRAM for desktops and servers from today’s DDR4 technology to DDR5. For future desktop/server applications, DRAM makers are developing, and plan to use, a range of new 3D DRAM technologies, such as High Bandwidth Memory (HBM) and the Hybrid Memory Cube (HMC).

Meanwhile, despite a push for LPDDR5, Wide I/O-2 is still alive and well. SK Hynix is developing Wide I/O-2 for mobile applications. Micron and Samsung are also exploring Wide I/O-2, although there are still several challenges to manufacture the 3D DRAM technology.

It’s also not a simple task to scale planar DRAM. To help make LPDDR5 happen and perhaps extend DDR4 SDRAMs, memory makers must scale planar DRAM from the current 2xnm node to the 1xnm regime, which is far beyond what was once considered possible.

“Can we stop DRAM development? No we can’t. In fact, the 10nm era is coming soon. But for the next node, we will need new technology,” said E.S. Jung, executive vice president of the semiconductor R&D center at Samsung, at a recent event.

For OEMs, there are two lingering questions. First, which technology —LPDDR4, LPDDR5, Wide I/O-2 or some other scheme — will dominate the mobile memory landscape in the future? And second, just how will the industry scale the planar DRAM beyond the magical 20nm barrier?

Mobile memory madness
At one time, the DRAM was a mere commodity, which was almost always in an oversupply mode. But after a major shakeout in the supplier base, the DRAM industry is booming and supply is tight right now.

In total, the DRAM market is projected to reach $45 billion in 2014, up 30% over 2013, according to TrendForce, a research firm. Not long ago, PCs accounted for 80% of all DRAM sales. But amid an explosion of smartphones and tablets in the market, mobile DRAMs will account for 40% of all DRAM sales in 2014, up from 14% in 2010, according to TrendForce.

To keep up with the bandwidth requirements in portables, OEMs traditionally have used mobile DRAMs based on LPDDR technology. But in 2008, LPDDR appeared to be running out of gas. At the time, the industry wanted a 3D TSV-based architecture called Wide I/O. But by 2012, Wide I/O fell by the wayside because it was too expensive and difficult to make.

Meanwhile, the industry continues to evolve LPDDR technology. Today, LPDDR3-based mobile DRAMs represent the mainstream memory technology for mobile products. LPDDR3 operates at 1.2 volts and has a data rate up to 15-GB/s.

Now, memory makers are ramping up LPDDR4-based mobile DRAMs, which operate at 1.1 volt and have a data rate up to 25.8-GB/s. “With LPDDR4, we are seeing a lot of interest outside the traditional mobile market,” said Daniel Skinner, director of mobile DRAM architecture at Micron. “LPDDR4, even more than LPDDR3, is going to find its way into PC applications, such as thin and light client laptops. We are also seeing interest in LPDDR4 for server/workstation applications, where traditional DDR is used.”

Still, DDR4-based SDRAMs will become the mainstream memory for the high-end, but DDR5 is up in the air. “There is still going to be a strong market for DDR4 for traditional memory, especially in high-performance computing,” Skinner said. “There are no definite plans for DDR5 PC memory. Instead, there are a lot of solutions emerging for the high-performance computing socket, including HMC and HBM.”

For mobile memory, meanwhile, what’s after LPDDR4? “Now, we are faced with a blank slate again,” Skinner said. “Can we extend the LPDDR architecture one more node, or do we have to do something more radically different like a Wide I/O device? Wide I/O has been trying to enter the mobile market for two generations. If all you cared about was power, then Wide I/O would have displaced LPDDR3 and LPDDR4. But Wide I/O comes with a lot of complications in terms of packaging technology and a business model.”

To hedge its bets, the industry is now looking at LPDDR5. In fact, the industry hopes to define the specifications for LPDDR5 by 2016. The devices are due out by 2017 or 2018. “There are several proposals that people have made semi-public at JEDEC for things they would like to explore for LPDDR5, but it’s very early,” he said.

Others also see the need for LPDDR5, but the timing for the technology remains still unclear. Mike Williams, vice president of memory product planning at Samsung, asked: “When will it happen? And what’s the alternative?”

The alternative is Wide I/O-2. But the industry is still waiting for a new memory application that could adopt Wide I/O-2, which in turn could help the technology get over the cost and energy curve, Williams said.

SK Hynix has a different take on LPDDR5. “It will take at least two to three years to define it,” said Sunny Khang, technical marketing director at SK Hynix. “By then, LPDDR5 might be too late. Plus, we’ve almost reached the limitations in thermal and signal integrity (with LPDDR technology in general). We are willing to join the discussions on LPDDR5, but we are more focused on Wide I/O-2. From a technical standpoint, Wide I/O-2 is more of a reasonable solution.”

In the second half of 2015, SK Hynix hopes to sample Wide I/O-2 devices, which operate at 1.1 volt and have a data rate up to 51.2-GB/s. But as before, there are several challenges with advanced chip stacking, namely thermal issues, supply chain headaches and cost.

So, will Wide I/O-2 succeed or not? It’s still too early to tell. The same holds true for LPDDR5. In theory, though, there might be room in the market for both Wide I/O-2 and LPDDR5 as the mobile market continues to explode.

Scaling the DRAM
If LPDDR5 moves forward, DRAM makers may need to scale planar DRAM to the 1xnm node, which is a challenging feat. Each planar DRAM cell is made up of a transistor and a capacitor. “For 20nm-class DRAMs, most of the manufacturers still use a B-CAT (buried channel array transistor) structure, a raised SiGe source/drain, and a bulky finFET active structure. A bulky finFET is a saddle-type structure, rather than a finFET structure (used in the logic market),” said Jeongdong Choe, a principal engineer/architect at TechInsights.

The DRAM capacitor, meanwhile, stores a bit of data in the device. A capacitor will discharge in a system over time, which means the charge must be refreshed several times each second. This, in turn, causes unwanted power consumption in systems.

Today’s leading-edge DRAMs are 20nm devices. To break the 20nm barrier, the industry will require new breakthroughs in four basic areas—patterning; scaling the DRAM capacitor; shrinking the cell size; and power consumption.

In patterning, DRAM makers continue to extend optical lithography. “The DRAM industry is marching towards 10nm,” said Gill Lee, senior director and a principal member of the technical staff at Applied Materials. “Major DRAM players are not counting on EUV in the near future. Basically, the DRAM industry is adopting more multiple patterning technologies at different levels. The cost for multiple patterning is not as expensive as before. That allows the DRAM guys to move below 20nm.”

Still, the single biggest challenge in DRAM production is clear—scaling the DRAM capacitor. The capacitor itself becomes smaller at each node. Yet the amount of charge within the capacitor must remain constant.

Originally, the DRAM capacitor resembled a 2D-like plate structure. Realizing the 2D structure was running out of steam several years ago, DRAM makers turned the capacitor into a vertical, cylindrical-like structure.

For the capacitor, the industry went to a metal-insulator-metal (MIM) stack using high-k dielectrics. High-k enables the structure to maintain its capacitance at low leakage. In many cases, the MIM capacitor stack in today’s DRAMs makes use of ZAZ technology, which represents Al2O3 materials sandwiched between two ZrO2 layers.

For 1xnm DRAMs, the capacitor may require next-generation, perovskite-based materials, which have ultra high-k properties. “None of these next-generation materials are really successful in terms of beating the existing ZAZ materials—yet,” said Applied’s Lee. “So, we will see more of an incremental modification of the existing materials. Of course, DRAM makers could have some magic materials in the pipeline. But even without those magic materials, the DRAM industry can still get close to the 10nm node.”

To scale the capacitor structure, DRAM makers require an etch process with high aspect ratios. It also requires atomic layer deposition (ALD) to fill the cylinders with materials. “If you think about it, DRAM has been a 3D device for the longest time, because the capacitors are vertical cylinders,” said Dave Hemker, senior vice president and chief technology officer at Lam Research.

“For the DRAM, we are drilling the hole, which is then filled. That becomes the capacitor. And then, we use ALD to get the dielectrics in,” Hemker said. “For the etch, I need a certain amount of volume to get the capacitance. In fact, DRAM requires the highest aspect ratios in the industry. Those can be at 60:1.”

Another goal is to shrink the DRAM cell size from 6F(square) today to the practical limit of 4F(square). “Everyone wants to make a 4F2 cell,” Applied’s Lee said. “If a 4F2 cell is realized, then the cell size at the same geometry is reduced by one third. So far, 4F² has not been successful. However, the 6F square concept has made it all the way to 20nm. And it looks like it will continue below the 20nm node.”

What’s next? For years, the industry has been working on the capacitor-less DRAM, but the technology is complex and still in the lab. “I don’t see the 1T DRAM becoming a major memory in the near future,” Lee said.

And if planar DRAM runs out of gas, OEMs could move to 3D DRAMs. In addition, the industry has been working on a possible DRAM replacement—the spin-torque MRAM. “Everyone would love for MRAM to work, but that is still a long way off for non-embedded standalone memory applications,” Lam’s Hemker said.