Why Investments At Advanced Nodes Matter

Despite all the talk about rising costs of development, uncertainties about lithography and talk about the death of Moore’s Law, a record number of companies are developing chips at 16nm/14nm. That may sound surprising, but asking why that’s happening is probably the wrong question. The really critical question is what they’re going to do with those chips.

What’s become quite evident in the semiconductor business is that learning from one node to the next is cumulative—part incremental, part evolutionary, part revolutionary, and since 28nm filled with uncertainties. You need all the knowledge from the previous nodes, plus a deep familiarity with all of the new twists and turns. Even if companies decide to stay at 28nm for the next three revs of Moore’s Laws, they can’t afford not to develop chips at the most advanced nodes. While 20nm planar chips proved to be relatively useless from a production standpoint—they cost more and they didn’t solve the current leakage issue—they did teach the industry how to do double patterning. At 16/14nm, the industry is learning about to work with finFETs, which means increased dynamic power density, thermal modeling and more process variation.

At 10nm, there will be multi-patterning—at least of some metal layers, possibly coupled with EUV on others—along with new materials and multi-patterned vias. And at 7nm, which is just getting started, there could be entirely new materials, transistors structures and interconnects.

You don’t get good at this stuff overnight. It takes years of development, working closely in teams with foundries and EDA companies, which are learning as they go along, as well. And if you lose the ability to create these chips, you’re at a competitive loss—possibly permanently. That’s why more companies are developing chips using TSMC’s 16nm finFETs (with a 20nm BEOL process), GlobalFoundries and Samsung’s 14nm finFETs (also with a 20nm BEOL process), and Intel’s 14nm finFETs (with a 14nm process).

There also is a simultaneous push into 2.5D and 3D ICs with the same fervor as the most advanced process nodes. Chipmakers are preparing for all possibilities, on the assumption that whichever way the industry goes, they will need to be ready. In an exclusive interview with Semiconductor Engineering, Intel’s Mark Bohr discusses his company’s alternative to an interposer, called an Embedded Multi-die Interconnect Bridge.

But what, exactly are they going to do with these chips? The answer may be high-volume production chips, but it might also be test chips or limited run chips for very narrow markets. But this is no ordinary question because the answer is worth tens of billions of dollars. This is what is keeping the foundry bean counters and the whole equipment industry wide awake at night. Do they take the plunge at 16nm/14nm and build an advanced fab, which is estimated to run between $5 billion and $7 billion, give or take $1 billion (the same sources of those estimates have quoted those and other numbers, sometimes in the same conversation). Will the volume be there to sustain it?

EUV, for all the notoriety it has garnered over the past four process nodes, is only one piece of the puzzle. It’s an important one, but it becomes less important as time goes on and other alternatives such as multi-beam, directed self-assembly gain ground. And it may become much less important at 7nm, where line widths are too small for even EUV, making double patterning a necessity.

So what will chipmakers do? Will they gain new knowledge while concentrating the bulk of their production at 28nm. Will they push up into stacked die, up and out into package-on-package fan-outs, down into 16/14nm, 10nm and 7nm. Or will they sit and wait on all of this stuff until someone takes the plunge and watch what happens. At this point, no one knows.