Why Test Costs Will Increase

The economics of test are under siege. Long seen as a necessary but rather mundane step in ensuring chip quality, or a way of testing circuitry from the inside while it is still in use, manufacturers and design teams have paid little attention to this part of the design-through-manufacturing flow.

But problems have been building for some time in three separate areas, and they could have a big effect on the economics of test.

First, new materials are being added into chips that need different testing approaches than in the past. Some of these materials can withstand extremely high temperatures, which is essential in annealing. Others are soft or brittle, particularly those used in thin films or for increased electron mobility. In addition, not all sources of materials are consistent, so impurities can creep into processes that could cause chip-killing defects at 7nm or 5nm.

To make matters worse, some of these materials can be damaged during processing, and some of them can be destroyed with existing test procedures. All of these new materials are man-made, and they are designed to have different behaviors than those used in the past. That, in turn, requires additional characterization, but not all of that characterization can be done up front. It also depends on how materials behave in the real world under a wide variety of use cases, and that data needs to be analyzed and fed back into test programs. This takes a lot of time and effort, and it pushes test much deeper into the planning process for chips than ever before.

That leads to the second factor. What was considered good enough in the past may not be good enough in the future. A chip that doesn’t meet spec typically is put into one or more bins and sold as an underperforming part for lower-cost devices. But as chips are added into autonomous vehicles or used in industrial applications, testing needs to be much more rigorous. Underperforming parts may not be allowed anywhere in an autonomous vehicle supply chain, where automakers are demanding parts last up to 17 years with zero defects.

Developing parts with this defect level requires much more extensive testing, and that slows down the whole manufacturing process. While some of this will have to be dealt with using some sort of self-test, that approach consumes area with extra circuitry. Depending upon the process geometry—think about a 7nm AI chip, for example—it can impact performance or increase power consumption.

That puts a huge demand on external testing, and the problem there is a combination of parallelization and coverage. More coverage requires more time, both in terms of writing design-for-test programs and the actual testing process, and it affects both design and fab schedules. that, in turn, drives demand for more test equipment, or more sophisticated test equipment, and pushes up the cost of developing new chips.

The third factor involves multi-chip packages, and test plays a significant role both before and after packaging. Known good die are a requirement in any package. A defect in any chip in a multi-chip package of any type—fan-out, 2.5D, SiP, MCM, monolithic 3D—can be fatal to all of the chips in that package, which raises the stakes for getting this right. Most of these packages are expensive to begin with, which is why most of them are in expensive devices such as smart phones and data center servers and networks. A 2.5D package connected to HBM is blazing fast, but it also has to work according to spec.

Testing chips in a package isn’t so simple, though. It takes more time, because it’s not just one chip being tested. With monolithic 3D, it requires following signals through two or more chips, with some layers not directly accessible to the testers. And if these chips are developed at 7nm or 5nm, it requires testing 3D structures within a multi-chip package.

Put all of these factors together and it appears very likely that test costs will begin creeping up. Longer-term reliability is becoming much more important in a variety of new and existing markets, and test is a critical factor in ensure that devices will work as planned.