5 Reasons EUV Will Or Won’t Be Used

Opinions about EUV abound following each new announcement — good or bad—but what is required to get a data-driven assessment of the technology status?

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Digging into this subject, there are five metrics that count in a lithography tool: resolution, throughput, defects, overlay, and reliability. So what does the best data tell us about the current state and realistic prognosis for EUV. Semiconductor Engineering posed this question to Matt Colburn, senior manager for patterning research at IBM, who coordinated these responses.

The short version seems to be that it is realistic that production (non beta) HVM exposure systems could be available in 2017 and shipping product in 2019. The unresolved issue list is pretty long, but the keys seem to be the light source, and solving the collective resolution-LER-throughput tradeoff. The pellicle issue seems to be receding based on pellicle research and process demonstrations without pellicles.

Colburn is a fellow imprint alumnus, and he is deeply involved in EUV developments at IBM. What follows are excerpts of this discussion.

SE: What is the demonstrated resist resolution?

Colburn: Current resolution capability demonstrated in resist from the EUVL Symposium is 12nm half pitch as presented by Inpria. (see reference 1) (www.inpria.com) The likely limit for 0.33NA in 2015 would be about 14nm half pitch using advanced illumination, the latest resist systems, and aggressive RETs. Below about 14nm half pitch, resolution improvements will be enabled either by multi-level patterning with the current lens, single layer with larger NA (see reference 2), or directed self-assembly (see reference 3).

SE: At what resolution is line edge roughness (LER) a non-issue. What is the realistic dose increase needed for either of these?

Colburn: For a 14nm half-pitch node, we believe that we can handle the LER with today’s dose levels. Our resists and post-processing technology are improving along with etch and film expertise. Beyond the 7nm node, we will have to see. It is likely we need to add another tool to the toolbox. Further, novel resist platforms (non-chemically amplified resists) are showing significant benefits in terms of resolution and LER performance (see reference 4).

SE: Cost competitive throughput is generally recognized as 100 wafers per hour, so how long will it take to get there?

Colburn: We can debate the crossover point endlessly (based on each customer’s installed tool base, product mix, mask lifetime, consumables, etc.), but 100 WPH is a good target. This is consistent with a recent statement by TSMC’s Burn Lin at SemiCon Taiwan 2014 that an EUV solution could be cost-competitive to immersion solutions at 125 watts (see reference 5). Cymer/ASML demonstrated 80 watts in October 2014 (see reference 6). It is expected that the 80 watts performance will deploy to the field in 2015. In the simplest estimate based on our endurance run, 80 watts would provide about 68 wafers power hour. Analogously, 125 watts would provide about 106 wafers per hour. It is expected that a 125-watt source will be demonstrated in the coming year with a defined path moving past that power level.

Takeaway: If 125 watts is demonstrated in 2015, it presumably will be beta installed in 2016, available for volume tool shipments in 2017. And this assumes no significant increase in dose to deal with LER.

SE: The critical question is what is the practical reality of running a fab without pellicles.

Colburn: Managing EUV mask defect adders will be key. The existing dual-pod approach does protect the mask while it is not being used to expose wafers in the scanner. At the EUVL Symposium, TSMC stated that more than 2500 wafer exposures were accomplished over a two-month period with no new defects added to the patterned area of the monitored mask (see reference 7). That said, there are strategies to identify and mitigate the impact of mask adders.

While pellicles haven’t been commercialized yet, ASML has demonstrated significant progress toward a viable EUV pellicle. Further, there continues to be progress in the area of pellicle research. While ASML is leading the field with confirmed imaging performance with a pellicle, multiple companies have shown pellicle proofs-of-concept. Collectively, the industry needs an open-source pellicle that can be mounted and is stable under EUV HVM-use conditions. We are still a long way from that goal, but progress in the last 12 months has been promising.

SE: Is the evidence that pellicle-free operation may be feasible a big factor in the recent TSMC commitment to EUV? Before you can fix defects you have to find them.

Colburn: Actinic EUV mask blank inspection capability has been demonstrated at EIDEC. Actinic patterned mask aerial image metrology system (AIMS) inspection has achieved first light and is on track for delivery of first customer systems in 2015 (see reference 8). Actinic EUV patterned mask inspection (PMI) has made progress in defining a design concept (see reference 9). Ultimately, using the printer as the inspection tool, coupled with wafer-based pattern inspection (e-beam and optical) can and will fill the gap until actinic PMI. In addition, the current 193nm EUV mask PMI tooling already is being used to inspect EUV masks and has been shown to capture the vast majority of the total defects that would be imaged at the wafer level (see reference 10).

SE: The trouble is that if a particle does land on the wrong place on the reticle, then a killer repeating defect is created and yield drops to zero until the defect is detected. So some form of continuous monitoring seems essential.

Colburn: Strategies for identification of repeaters in both small and full-field die are underway that optimize inspection time and minimize cost of goods in build.

SE: What about blank defects?

Colburn: Blanks are nearing the development target (see reference 11) and Sematech has demonstrated a new technique that I expect to be adopted. Further progress must be made in commercialization.

SE: How about patterned reticle quality?

Colburn: Beyond incoming blank defects, patterned mask quality is sufficient for development at this stage. As discussed in the previous section, inspection and repair during the fabrication requires additional technology maturation, which will come with increased mask volumes.

SE: And reticle repair?

Colburn: Reticle repair flows have been demonstrated in a research flow using SHARP, although actinic inspection and EUV AIMS will make it more practical. Further, blank defect repair, coupled with defect avoidance, approaches have been demonstrated although not commercialized (see reference 12).

SE: The exposure wavelength has very little impact on the overlay, so the overlay of state of the art 193nm tools and EUV can be expected to be the same.

Colburn: EUV overlay is already demonstrated at equivalent performance to ArFi. However, EUV presents a unique opportunity to improve device yield/performance by reducing the composite errors currently accumulated (from multi-patterning). At AVS 2014, IBM presented a comparison between optical and EUV patterning, which demonstrated improved electrical variation for a representative 10nm technology node metal structure with EUV (see reference 13).

SE: The latest benchmark is a first 24-hour operation. There is a long way from here to HVM grades of reliability.

Colburn: From our experience at IBM in the publicized reliability runs, the ‘laws of physics’ issues are not the limiters at this point. That being said, there is a lot of work to be done to achieve HVM performance targets.

SE: What is your projection on availability?

Colburn: There are defined plans to achieve availability targets. Availability is a matter of maturing new elements and ensuring robust integration into the overall system. We believe 7nm half pitch is the right time for insertion. The recent announcement of addition NXE-3350 purchases slated for 2015, as well as comments made at EUVL Symposium, bolsters this stance (see reference 14).

Conclusions and observations
Reliable 100 wph HVM systems in 2017 seem realistic, with product shipments in 2019. But will it be a pellicle or pellicle-free operation? This is the big surprise. The TSMC data makes pellicle-free operation look realistic. The Industry pellicle effort is accelerating. The industry needs to keep a keen eye on the mask technology.

Other observations:

• Line edge roughness at target sensitivity remains for a question for which there is limited published data.

• Defect inspection and defect elimination in reticles and patterned wafers also looks realistic, but commercial inspection systems lag the litho tool.

• Certainly the decision from TSMC, which has been EUV sceptics for many years, to purchase multiple systems is a milestone event.

REFERENCES

    1. S. Tagawa, etal “High-resist sensitization by pattern and flood combination lithography” Proc of SPIE. Vol 9048, 2015
    2. B. J. Lin – TSMC SEMICON Taiwin 2014; B. J. Lin, “Making lithography work for the 7nm node and beyond.” MNE, 2014
    3. R. Peeters, “EUV lithography, NXE platform performance overview.” EUV Symposium 2014 (80W Source)
    4. Verbal comment during TSMC Plenary, 2500 wafers without particle addition. EUV Symposium 2014
    5. AIMS, Public Announcement; Zeiss Corporation Press Release “Significant progress achieved in AIMS EUV Project.” Feb. 19, 2014 DD SPIE ARTICLE
    6. KT Actinic announcement (Bacus 2014)
    7. W. Broadbent, et al “EUV reticle inspection with a 193nm reticle inspector. “ Proc. SPIE 8701, 87010W (June 28, 2013)
    8. Sematech EUV Mask Blank Press Release; A. Tchikoulaeva, et.al. “EUV actinic blank inspection: from prototype to production” Proc. SPIE 8679, Extreme Ultraviolet (EUV) Lithography IV, 86790I (April 1, 2013)
    9. E. Gallagher et al, “EUV Masks: ready or not?” EUV Symposium 2011; E. Gallagher et.al., “Learning from native defects on EUV mask blanks.” Proc SPIE 9 can 56 (2014)
    10. J. Shearer et.al., “Contact Level Patterning Challenges for Sub 22-nm Architecture,” AVS 2014
    11. Esin Terzioglu (Qualcomm) Abstract & Verbal Communication Plenary Presentation, EUV Symposium 2014 Plenary Presentation. “With key decisions occurring by 2H2015 on design rules and cell architectures for the 7nm node, the entire EUV ecosystem must be brought to a state of readiness in that timeframe to raise the confidence level of a full commitment to EUV lithography in 7nm node. One key strategy for driving readiness is to optionally introduce EUV on limited mask levels for a 10nm product designed with 193i lithography, ahead of full EUV ramp on the 7nm node.”
    12. E. Gallagher et al, “EUV Masks: ready or not?” EUV Symposium 2011; E. Gallagher etal, “Learning from native defects on EUV mask blanks,” Proc SPIE 9can 56 (2014)
    13. J. Shearer etal, “Contact Level Patterning Challenges for Sub 22-nm Architecture,” AVS 2014
    14. Esin Terzioglu (Qualcomm) Abstract & Verbal Communication Plenary Presentation, EUV Symposium 2014 Plenary Presentation. “With key decisions occurring by 2H2015 on design rules and cell architectures for the 7nm node, the entire EUV ecosystem must be brought to a state of readiness in that timeframe to raise the confidence level of a full commitment to EUV lithography in 7nm node. One key strategy for driving readiness is to optionally introduce EUV on limited mask levels for a 10nm product designed with 193i lithography, ahead of full EUV ramp on the 7nm node.”


  • Gary

    Mike at the end of the day will costs come down with EUV implementation as advanced nodes are achieved, or will the cost performance curve begin to trend up. Does EUV become a mainstream enabler or an expensive solution to the more unusual need. What’s your take.