Process variation becomes more pronounced in low-power designs, requiring a different methodology for library characterization and variation modeling.
At 16nm and below, on-chip variation (OCV) becomes a critically important issue. Increasing process variation makes a larger impact on timing, which becomes more pronounced in low-power designs with ultra-low voltage operating conditions. In this paper, we will discuss how a new methodology involving more accurate library characterization and variation modeling can reduce timing margins in library files to account for these process variation effects. The paper will show how better library characterization can result in reduced timing pessimism to accelerate timing signoff.
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