No Two Chips Are Alike


As semiconductor processes continue to shrink it’s becoming increasingly challenging to manage the parameters of individual devices not only across the diameter of the wafer, but also across the length of a single chip, especially for a complex chip with a large area. Today’s standard approach to this problem is to assume the worst case and to create a sub-optimal design that accommodates t... » read more

Tech Talk: On-Chip Variation


Raymond Nijssen, vice president of systems engineering at Achronix, discusses on-chip and process variation at 7nm and 5nm, the role of embedded FPGAs, and how to reduce margin and pessimistic designs. https://youtu.be/LQnw_3H9soQ » read more

Addressing Process Variation And Reducing Timing Pessimism At 16nm And Below


At 16nm and below, on-chip variation (OCV) becomes a critically important issue. Increasing process variation makes a larger impact on timing, which becomes more pronounced in low-power designs with ultra-low voltage operating conditions. In this paper, we will discuss how a new methodology involving more accurate library characterization and variation modeling can reduce timing margins in libr... » read more

Multi-Source CTS Delivers Flexible High Performance and Variation Tolerance


Multi-source clock tree is a hybrid containing the best aspects of a conventional clock tree and a pure clock mesh. This paper illustrates the benefits such as lower skew and better on-chip-variation (OCV) performance compared to a conventional clock tree. To download this white paper, click here. » read more