Beyond Moore’s Law

The viability of shrinking features will end in 2020. So what will replace it? Here are some options.

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What do you make of all the different reports coming out of Advanced Lithography 2014 — the end of Moore’s Law, continued problems with EUV, directed self-assembly assembly makes progress? An equipment insider, whose judgment I value, came back from the meeting and concluded, “We will see the end of Moore’s Law shrinks in 2020. After that, no one knows!” There is no way a $300B+ business suddenly is going to stall, so what are the options?

In 1980, the industry used 100mm wafers, equipment cost $1M, ran at 30 wafers an hour, critical dimensions were 4 µm, in devices with 7 mask levels, and a typical memory cell was roughly 20 critical dimension (cd²), with yields of 30%.

In 2010, the industry used 300mm wafers, equipment cost $30M, ran at 100 wafers an hour, critical dimensions were 40 nm, in devices with 35 mask levels, and a typical memory cell was roughly 6 cd², with yields of 90%. A huge transformation in process and technology.

If I simply look at changes, the productivity has increased through wafer area by 9x, wafer throughput by 3x, through smaller transistors by 10,000x, by smaller memory cells by 3x, with 3x improved yield. These are offset by increased equipment costs of 30x, and increased mask levels by 5x. The net change in $ per transistor is 16,000x. In 20 years of Moore’s law, at 2x every 2 years, the change is $ per transistor is 32,000x, in pretty good agreement with my very crude bottom-up analysis.

The obvious takeaway from these developments is that the 10,000x cd shrink has been the main driver, but there has been another 250x in improvements to offset the 150x losses due to increased complexity of process and equipment.

Looking forward, the end of traditional shrinks is in sight simply because we are running out of atoms. Based on the Advanced Litho discussion, the latest ITRS road map for 2020 shows 13nm half pitch (30 atoms), which appears to be the end of the line for shrinks.

To go below 13 nm will require a completely different device that somehow we magically learn to yield at some ludicrously low defect level. This seems unlikely, so the answer has to be growth in the third dimension, which means adding mask levels and costs. At least the huge investments in new technology to print smaller features will go away, along with the exponential increases in equipment costs. Simply put, to keep going each doubling in density will require double the mask levels with a doubling in cost. Increases in functionality will not support this for long.

The first way to simplify lithography vertically is by self-assembly. Self-assembly in the horizontal plane is being enabled by the drive to simplify pattern shapes into blocks of parallel lines that allow patterning nearer the resolution limit. These parallel lines can be created in large arrays using block copolymers, delivering 2x or 4x multiplication of coarser patterns. In addition, research teams have shown how imprinted recesses can be used to guide self alignment, even creating breaks in lines.

An alternative is multi-layer patterning, which involves creating multilayers in a single operation. The HP SAIL process is at least one way to accomplish this using a single multi-step imprint to create multiple layers that are self aligned. The technology has been applied to large Thin Film Transistors, but there is no reason that a version could not be applied to nano features. Grant Willson’s team at the University of Texas has completed some feasibility demos f0r using imprint to create both via and interconnect with a single imprint.
So my forecast (or flat out guess) is that a combination of multilayer imprint and self assembly could be used to create 3D arrays of transistors and interconnects at lower cost. It would be an extension of today’s technology and can use today’s defect learning. It is also easy to see how this could be extended to multiple iterations of improvement.

A more speculative approach uses bio concepts to self-assemble. Our brains are a spectacular example of self-assembly. Our DNA provides the template, and a hierarchy of process create a spherical neural net that gets its compute power by exceptional parallel processing.

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Obviously we are not going to jump to a synthetic brain, but there are individual bio steps that could be used. Antibody binding is a way that specific proteins attach to specific locations on cell walls. Antibody tags have been used to attach gold nano-spheres to surfaces, and localized binding can be used to block attachment in certain areas. Now you can imagine self-assembled sets of lines with antibody tags to pattern other multiple layers.

My takeaway is that stacked 3D devices will take over the increase in transistor counts, and that there are realistic ways to cut costs in the near future. The current drive for pattern simplification for multi-patterning is putting in place the changes in devices and design tools that will be needed for self-assembly. Oh, and maybe imprint will be a key.  But then, I may be a bit biased !