Tech Talk: 7nm Litho

David Fried, chief technology officer at Coventor, digs into future scaling issues involving multi-patterning and new transistor types. Related Stories Faster Time To Yield Coventor’s CEO talks about how to get chips through manufacturing more quickly. » read more

Tech Talk: FD-SOI vs. FinFET

Jamie Schaeffer, 22FDX program director at GlobalFoundries, talks about the future of FD-SOI, what the tradeoffs are in performance, power and cost compared with finFETs, how many mask layers and patterning steps are required for each, and when 12nm FD-SOI will be introduced. Related Stories To 7nm And Beyond GlobalFoundries’ top technologists open up on next-gen FD-SOI, the economi... » read more

Tech Talk: Embedded Memories

Dave Eggleston, vice president of embedded memory at GlobalFoundries, talks about the pros and cons of new types of embedded memory, including which work best for certain applications and with various advanced packaging options. [youtube vid=7D9zoA9FFIw] » read more

Tech Talk: GPU-Accelerated Photomasks

Noriaki Nakayamada, group manager for the data control engineering group in NuFlare's Mask Lithography engineering Department, talks about what's changing on the mask side, where the trouble spots are, and how to deal with them at advanced process nodes. [youtube vid=f8PixJMadXw] » read more

Tech Talk: Double-Triple Patterning

Mentor Graphics' David Abercrombie shows the differences and challenges in double patterning versus triple patterning. [youtube vid= e0wZmjBbEf0] » read more

Tech Talk: 14nm And Stacked Die

Aashish Malhotra, marketing director for the ASIC Business Unit at GlobalFoundries, talks about 14nm process technology, the IP ecosystem, and why that technology node will be used as a platform for 2.5D and 3D stacked die across a wide range of markets including the Internet of Everything. [youtube vid=ukTRuedB7ZU] » read more

Tech Talk: 10nm Patterning

David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics, talks about triple and quadruple patterning after 20/16/14nm and what design teams need to understand to get this right. [youtube vid=7bjutPWakpw] » read more

Tech Talk: Wafer Plane Analysis

Leo Pang, executive vice president at D2S, talks about the problems of patterning at 40nm and below and how to deal with them more effectively using existing equipment. [youtube vid=FbRyhw2q3fE] » read more

Tech Talk: 22nm FD-SOI

Subramani Kengeri, vice president of global design solutions at GlobalFoundries, discusses the evolution of 22nm FD-SOI and its advantages, including single patterning in the middle end of line, 0.4 volt operating voltage, and how it compares to finFETs in terms of performance. [youtube vid=5fa1AcIGcUw] » read more

Tech Talk: 14nm

Tamer Ragheb, digital design methodology technical lead at GlobalFoundries about what's changed with 14nm finFETs, including coloring with double patterning, new corners, Miller Effects, timing issues and variability. [youtube vid=Yk6jSKCtsjU] » read more

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